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[Test] Update test case which uses counter benchmarks: adding pin constraints

This commit is contained in:
tangxifan 2022-02-15 16:29:06 -08:00
parent 430580f138
commit 8be0868a3b
3 changed files with 10 additions and 3 deletions
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4
openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
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@ -55,9 +55,9 @@ write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
# Write the SDC files for PnR backend
# - Turn on every options here

7
openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/pin_constraints_reset.xml Normal file
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@ -0,0 +1,7 @@
<pin_constraints>
<!-- For a given .blif file, we want to assign
- the reset signal to the op_reset[0] port of the FPGA fabric
-->
<set_io pin="reset[0]" net="reset"/>
</pin_constraints>

2
openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf
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@ -30,7 +30,7 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/c
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = counter
bench0_chan_width = 300
bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=