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[Test] Update bus group file due to little and big endian conversion during yosys/vpr

This commit is contained in:
tangxifan 2022-02-18 15:02:08 -08:00
parent 36543f7f2f
commit b4d59fdd1e
1 changed files with 8 additions and 8 deletions
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16
openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_explicit_mapping/config/counter8_bus_group.xml
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@ -1,12 +1,12 @@
<bus_group>
<bus name="result[0:7]">
<pin id="0" name="result_0_"/>
<pin id="1" name="result_1_"/>
<pin id="2" name="result_2_"/>
<pin id="3" name="result_3_"/>
<pin id="4" name="result_4_"/>
<pin id="5" name="result_5_"/>
<pin id="6" name="result_6_"/>
<pin id="7" name="result_7_"/>
<pin id="0" name="result_7_"/>
<pin id="1" name="result_6_"/>
<pin id="2" name="result_5_"/>
<pin id="3" name="result_4_"/>
<pin id="4" name="result_3_"/>
<pin id="5" name="result_2_"/>
<pin id="6" name="result_1_"/>
<pin id="7" name="result_0_"/>
</bus>
</bus_group>