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[Flow] Patch new test case

This commit is contained in:
tangxifan 2022-01-02 20:20:36 -08:00
parent 48355d1fc3
commit 824a03bdca
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8_reg/config/task.conf
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@ -30,13 +30,13 @@ openfpga_vpr_device_layout=3x2
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2_pipelined/mac_2_pipelined.v
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult_2_pipelined/mult_2_pipelined.v
[SYNTHESIS_PARAM]
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = mac_2_pipelined
bench0_top = mult_2_pipelined
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=