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[HDL] update dff map rules to support negative triggered ffs

This commit is contained in:
tangxifan 2022-05-09 16:58:18 +08:00
parent 22c4d72358
commit 0afe3a6d33
1 changed files with 6 additions and 6 deletions
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12
openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
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@ -47,21 +47,21 @@ endmodule
// The following techmap operation are not performed right now
// as Negative edge FF are not legalized in synth_quicklogic for qlf_k6n10
// but in case we implement clock inversion in the future, the support is ready for it.
module \$_DFF_N_ (D, C, Q);
module \$_DFF_N_ (D, CN, Q);
input D;
input C;
input CN;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(CN));
endmodule
module \$_DFF_NP0_ (D, C, R, Q);
module \$_DFF_NP0_ (D, CN, R, Q);
input D;
input C;
input CN;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
dffr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(CN), .R(R));
endmodule
module \$_DFFE_NP0P_ (D, C, E, R, Q);