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[Arch] Bug fix on architecture with registerable DSP

This commit is contained in:
tangxifan 2022-01-02 20:35:48 -08:00
parent f667065f75
commit e3baec63f8
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
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@ -83,8 +83,8 @@
<!-- Highly recommand to customize pin location when direct connection is used!!! -->
<!-- pinlocations are designed to spread pin on 4 sides evenly -->
<pinlocations pattern="custom">
<loc side="left">mult_8.a[0:3] mult_8.a[0:3] mult_8.out[0:7]</loc>
<loc side="top"></loc>
<loc side="left">mult_8.a[0:3] mult_8.b[0:3] mult_8.out[0:7]</loc>
<loc side="top">mult_8.clk</loc>
<loc side="right">mult_8.a[4:7] mult_8.b[4:7] mult_8.out[8:15]</loc>
<loc side="bottom"></loc>
</pinlocations>