diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
index d7e9028d5..5fad1aba2 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
@@ -83,8 +83,8 @@
       <!--  Highly recommand to customize pin location when direct connection is used!!! -->
       <!-- pinlocations are designed to spread pin on 4 sides evenly -->
       <pinlocations pattern="custom">
-        <loc side="left">mult_8.a[0:3] mult_8.a[0:3] mult_8.out[0:7]</loc>
-        <loc side="top"></loc>
+        <loc side="left">mult_8.a[0:3] mult_8.b[0:3] mult_8.out[0:7]</loc>
+        <loc side="top">mult_8.clk</loc>
         <loc side="right">mult_8.a[4:7] mult_8.b[4:7] mult_8.out[8:15]</loc>
         <loc side="bottom"></loc>
       </pinlocations>