[test] update golden outputs for no_cout_in_gsb testcase
This commit is contained in:
tangxifan
parent
a88bc2d4de
commit
513f7800aa
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@ -50,7 +50,7 @@ module and2_top_formal_verification_random_tb;
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initial begin
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clk[0] <= 1'b0;
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while(1) begin
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#0.5561901927
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#0.4485172927
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clk[0] <= !clk[0];
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end
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end
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@ -109,7 +109,7 @@ initial begin
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$timeformat(-9, 2, "ns", 20);
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$display("Simulation start");
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// ----- Can be changed by the user for his/her need -------
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#7.786663055
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#6.279242039
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if(nb_error == 0) begin
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$display("Simulation Succeed");
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end else begin
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File diff suppressed because it is too large
Load Diff
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@ -45,14 +45,14 @@ wire [0:0] clk_fm;
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// ----- End Connect Global ports of FPGA top module -----
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// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
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// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] -----
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assign gfpga_pad_GPIO_PAD_fm[12] = a[0];
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// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[39] -----
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assign gfpga_pad_GPIO_PAD_fm[39] = a[0];
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// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[9] -----
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assign gfpga_pad_GPIO_PAD_fm[9] = b[0];
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// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[48] -----
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assign gfpga_pad_GPIO_PAD_fm[48] = b[0];
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// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[11] -----
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assign c[0] = gfpga_pad_GPIO_PAD_fm[11];
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// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[34] -----
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assign c[0] = gfpga_pad_GPIO_PAD_fm[34];
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// ----- Wire unused FPGA I/Os to constants -----
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assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
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@ -64,7 +64,10 @@ wire [0:0] clk_fm;
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assign gfpga_pad_GPIO_PAD_fm[6] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[7] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
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@ -86,12 +89,10 @@ wire [0:0] clk_fm;
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assign gfpga_pad_GPIO_PAD_fm[31] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[32] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[33] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[34] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[35] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[36] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[37] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[38] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[39] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[40] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[41] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[42] = 1'b0;
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@ -100,7 +101,6 @@ wire [0:0] clk_fm;
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assign gfpga_pad_GPIO_PAD_fm[45] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[46] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[47] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[48] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[49] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[50] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[51] = 1'b0;
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@ -316,14 +316,14 @@ initial begin
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_outb[0:2] = 3'b110;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = {17{1'b0}};
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = {17{1'b1}};
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = 17'b00000000110000001;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = 17'b11111111001111110;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:2] = 3'b001;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:2] = 3'b110;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:3] = 4'b0001;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:3] = 4'b1110;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0001;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1110;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0010;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1101;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:2] = 3'b001;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
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@ -354,10 +354,10 @@ initial begin
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:9] = 10'b1111111110;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:9] = 10'b0000000001;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:9] = 10'b1111111110;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b0000000001;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b1111111110;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b0000000001;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b1111111110;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b0001001000;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b1110110111;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b0010001000;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b1101110111;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:9] = 10'b0000000001;
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force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:9] = 10'b1111111110;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = {17{1'b0}};
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@ -396,14 +396,14 @@ initial begin
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_outb[0:2] = 3'b110;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = 17'b00000000110000001;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = 17'b11111111001111110;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = {17{1'b0}};
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = {17{1'b1}};
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:2] = 3'b001;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:2] = 3'b110;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:3] = 4'b0001;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:3] = 4'b1110;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0010;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1101;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0001;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1110;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:2] = 3'b001;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
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@ -434,10 +434,10 @@ initial begin
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:9] = 10'b1111111110;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:9] = 10'b0000000001;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:9] = 10'b1111111110;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b1000010000;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b0111101111;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b1000000100;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b0111111011;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b0000000001;
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force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b1111111110;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b0000000001;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b1111111110;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:9] = 10'b0000000001;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:9] = 10'b1111111110;
|
||||
force U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -462,8 +462,8 @@ initial begin
|
|||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -508,8 +508,8 @@ initial begin
|
|||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -586,8 +586,8 @@ initial begin
|
|||
force U0_formal_verification.sb_0__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -624,8 +624,8 @@ initial begin
|
|||
force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:7] = 8'b00100100;
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:7] = 8'b11011011;
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:5] = 6'b010001;
|
||||
|
|
@ -694,12 +694,12 @@ initial begin
|
|||
force U0_formal_verification.sb_1__1_.mem_top_track_0.mem_outb[0:7] = 8'b10111110;
|
||||
force U0_formal_verification.sb_1__1_.mem_top_track_8.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_1__1_.mem_top_track_8.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_out[0:7] = 8'b00101000;
|
||||
force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_outb[0:7] = 8'b11010111;
|
||||
force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_0.mem_out[0:7] = 8'b01000001;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_0.mem_outb[0:7] = 8'b10111110;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_out[0:7] = 8'b01001000;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_outb[0:7] = 8'b10110111;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_16.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_16.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:7] = 8'b01000001;
|
||||
|
|
@ -716,18 +716,18 @@ initial begin
|
|||
force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:7] = 8'b10001000;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:7] = 8'b01110111;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:5] = 6'b010010;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_outb[0:5] = 6'b101101;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:5] = 6'b010001;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_outb[0:5] = 6'b101110;
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -762,12 +762,12 @@ initial begin
|
|||
force U0_formal_verification.sb_2__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_1.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_outb[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -798,8 +798,8 @@ initial begin
|
|||
force U0_formal_verification.sb_2__1_.mem_left_track_3.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_5.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_5.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_7.mem_out[0:5] = 6'b000010;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_7.mem_outb[0:5] = 6'b111101;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_7.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_7.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -812,8 +812,8 @@ initial begin
|
|||
force U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -834,8 +834,8 @@ initial begin
|
|||
force U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_13.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -900,10 +900,10 @@ initial begin
|
|||
force U0_formal_verification.cbx_1__2_.mem_bottom_ipin_7.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -914,8 +914,8 @@ initial begin
|
|||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:5] = 6'b010100;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_outb[0:5] = 6'b101011;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_out[0:5] = 6'b000001;
|
||||
|
|
@ -934,8 +934,8 @@ initial begin
|
|||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_out[0:5] = 6'b000001;
|
||||
|
|
@ -944,8 +944,8 @@ initial begin
|
|||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_1.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_2.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_2.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_3.mem_out[0:5] = 6'b001100;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_3.mem_outb[0:5] = 6'b110011;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_3.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_3.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_4.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_4.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_5.mem_out[0:5] = 6'b000001;
|
||||
|
|
@ -1062,8 +1062,8 @@ initial begin
|
|||
force U0_formal_verification.cby_2__2_.mem_left_ipin_6.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cby_2__2_.mem_left_ipin_7.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cby_2__2_.mem_left_ipin_7.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_out[0:5] = 6'b010100;
|
||||
force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_outb[0:5] = 6'b101011;
|
||||
force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cby_2__2_.mem_right_ipin_2.mem_out[0:5] = 6'b000001;
|
||||
|
|
|
|||
|
|
@ -407,13 +407,13 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
|
|
@ -423,12 +423,12 @@
|
|||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
|
|
@ -457,9 +457,10 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -471,12 +472,11 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
|
|
@ -613,10 +613,10 @@
|
|||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
|
|
@ -624,15 +624,15 @@
|
|||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -773,11 +773,11 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
|
|
@ -829,8 +829,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -851,6 +850,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
|
|
@ -927,13 +927,10 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -943,7 +940,10 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1083,26 +1083,26 @@
|
|||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1327,17 +1327,11 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
|
|
@ -1345,6 +1339,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1356,6 +1351,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1371,10 +1369,12 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1945,8 +1945,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2041,12 +2041,12 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2211,8 +2211,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
|
|
@ -2227,20 +2227,20 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
|
|
@ -2253,7 +2253,7 @@
|
|||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
|
|
@ -2281,10 +2281,10 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
|
|
@ -2311,7 +2311,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2333,7 +2332,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2362,7 +2362,7 @@
|
|||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
|
|
|
|||
|
|
@ -818,19 +818,19 @@
|
|||
</bit>
|
||||
<bit id="1966" value="0" path="fpga_top.sb_1__1_.mem_right_track_16.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1965" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[7]">
|
||||
<bit id="1965" value="1" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="1964" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="1963" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1962" value="1" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[4]">
|
||||
<bit id="1962" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="1961" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1960" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1959" value="1" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[1]">
|
||||
<bit id="1959" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1958" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -850,17 +850,17 @@
|
|||
</bit>
|
||||
<bit id="1950" value="0" path="fpga_top.sb_1__1_.mem_right_track_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1949" value="0" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[7]">
|
||||
<bit id="1949" value="1" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="1948" value="0" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="1947" value="0" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1946" value="1" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[4]">
|
||||
<bit id="1946" value="0" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="1945" value="0" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1944" value="1" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[2]">
|
||||
<bit id="1944" value="0" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1943" value="0" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -918,11 +918,11 @@
|
|||
</bit>
|
||||
<bit id="1916" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1915" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[9]">
|
||||
<bit id="1915" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[9]">
|
||||
</bit>
|
||||
<bit id="1914" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[8]">
|
||||
</bit>
|
||||
<bit id="1913" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[7]">
|
||||
<bit id="1913" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="1912" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[6]">
|
||||
</bit>
|
||||
|
|
@ -936,9 +936,9 @@
|
|||
</bit>
|
||||
<bit id="1907" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1906" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0]">
|
||||
<bit id="1906" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1905" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[9]">
|
||||
<bit id="1905" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[9]">
|
||||
</bit>
|
||||
<bit id="1904" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[8]">
|
||||
</bit>
|
||||
|
|
@ -946,7 +946,7 @@
|
|||
</bit>
|
||||
<bit id="1902" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="1901" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[5]">
|
||||
<bit id="1901" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1900" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[4]">
|
||||
</bit>
|
||||
|
|
@ -956,7 +956,7 @@
|
|||
</bit>
|
||||
<bit id="1897" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1896" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0]">
|
||||
<bit id="1896" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1895" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[9]">
|
||||
</bit>
|
||||
|
|
@ -1230,9 +1230,9 @@
|
|||
</bit>
|
||||
<bit id="1760" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1759" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[3]">
|
||||
<bit id="1759" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1758" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[2]">
|
||||
<bit id="1758" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1757" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -1252,7 +1252,7 @@
|
|||
</bit>
|
||||
<bit id="1749" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1748" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[16]">
|
||||
<bit id="1748" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[16]">
|
||||
</bit>
|
||||
<bit id="1747" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[15]">
|
||||
</bit>
|
||||
|
|
@ -1266,9 +1266,9 @@
|
|||
</bit>
|
||||
<bit id="1742" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[10]">
|
||||
</bit>
|
||||
<bit id="1741" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[9]">
|
||||
<bit id="1741" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[9]">
|
||||
</bit>
|
||||
<bit id="1740" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[8]">
|
||||
<bit id="1740" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[8]">
|
||||
</bit>
|
||||
<bit id="1739" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[7]">
|
||||
</bit>
|
||||
|
|
@ -1550,15 +1550,15 @@
|
|||
</bit>
|
||||
<bit id="1600" value="0" path="fpga_top.cby_2__2_.mem_right_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1599" value="0" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[5]">
|
||||
<bit id="1599" value="1" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1598" value="0" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="1597" value="1" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[3]">
|
||||
<bit id="1597" value="0" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1596" value="0" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1595" value="1" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[1]">
|
||||
<bit id="1595" value="0" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1594" value="0" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -1662,9 +1662,9 @@
|
|||
</bit>
|
||||
<bit id="1544" value="0" path="fpga_top.cbx_2__1_.mem_bottom_ipin_5.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1543" value="1" path="fpga_top.cbx_2__1_.mem_bottom_ipin_4.mem_out[1]">
|
||||
<bit id="1543" value="0" path="fpga_top.cbx_2__1_.mem_bottom_ipin_4.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1542" value="1" path="fpga_top.cbx_2__1_.mem_bottom_ipin_4.mem_out[0]">
|
||||
<bit id="1542" value="0" path="fpga_top.cbx_2__1_.mem_bottom_ipin_4.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1541" value="0" path="fpga_top.cbx_2__1_.mem_bottom_ipin_3.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -1694,9 +1694,9 @@
|
|||
</bit>
|
||||
<bit id="1528" value="0" path="fpga_top.sb_2__1_.mem_left_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1527" value="0" path="fpga_top.sb_2__1_.mem_left_track_7.mem_out[5]">
|
||||
<bit id="1527" value="1" path="fpga_top.sb_2__1_.mem_left_track_7.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1526" value="1" path="fpga_top.sb_2__1_.mem_left_track_7.mem_out[4]">
|
||||
<bit id="1526" value="0" path="fpga_top.sb_2__1_.mem_left_track_7.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="1525" value="0" path="fpga_top.sb_2__1_.mem_left_track_7.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -1858,13 +1858,13 @@
|
|||
</bit>
|
||||
<bit id="1446" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1445" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[9]">
|
||||
<bit id="1445" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[9]">
|
||||
</bit>
|
||||
<bit id="1444" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[8]">
|
||||
</bit>
|
||||
<bit id="1443" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="1442" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[6]">
|
||||
<bit id="1442" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="1441" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[5]">
|
||||
</bit>
|
||||
|
|
@ -1872,25 +1872,25 @@
|
|||
</bit>
|
||||
<bit id="1439" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1438" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[2]">
|
||||
<bit id="1438" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1437" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1436" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1435" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[9]">
|
||||
<bit id="1435" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[9]">
|
||||
</bit>
|
||||
<bit id="1434" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[8]">
|
||||
</bit>
|
||||
<bit id="1433" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="1432" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[6]">
|
||||
<bit id="1432" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="1431" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1430" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="1429" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[3]">
|
||||
<bit id="1429" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1428" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -2170,9 +2170,9 @@
|
|||
</bit>
|
||||
<bit id="1290" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1289" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[3]">
|
||||
<bit id="1289" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1288" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[2]">
|
||||
<bit id="1288" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1287" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -2192,7 +2192,7 @@
|
|||
</bit>
|
||||
<bit id="1279" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1278" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[16]">
|
||||
<bit id="1278" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[16]">
|
||||
</bit>
|
||||
<bit id="1277" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[15]">
|
||||
</bit>
|
||||
|
|
@ -2206,9 +2206,9 @@
|
|||
</bit>
|
||||
<bit id="1272" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[10]">
|
||||
</bit>
|
||||
<bit id="1271" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[9]">
|
||||
<bit id="1271" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[9]">
|
||||
</bit>
|
||||
<bit id="1270" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[8]">
|
||||
<bit id="1270" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[8]">
|
||||
</bit>
|
||||
<bit id="1269" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[7]">
|
||||
</bit>
|
||||
|
|
@ -2658,15 +2658,15 @@
|
|||
</bit>
|
||||
<bit id="1046" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1045" value="1" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[5]">
|
||||
<bit id="1045" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1044" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="1043" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[3]">
|
||||
<bit id="1043" value="1" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1042" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1041" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[1]">
|
||||
<bit id="1041" value="1" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1040" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -2706,11 +2706,11 @@
|
|||
</bit>
|
||||
<bit id="1022" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1021" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_2.mem_out[1]">
|
||||
<bit id="1021" value="1" path="fpga_top.cbx_2__0_.mem_bottom_ipin_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1020" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_2.mem_out[0]">
|
||||
<bit id="1020" value="1" path="fpga_top.cbx_2__0_.mem_bottom_ipin_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1019" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_1.mem_out[1]">
|
||||
<bit id="1019" value="1" path="fpga_top.cbx_2__0_.mem_bottom_ipin_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1018" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -2742,7 +2742,7 @@
|
|||
</bit>
|
||||
<bit id="1004" value="0" path="fpga_top.sb_2__0_.mem_left_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1003" value="0" path="fpga_top.sb_2__0_.mem_left_track_7.mem_out[1]">
|
||||
<bit id="1003" value="1" path="fpga_top.sb_2__0_.mem_left_track_7.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1002" value="0" path="fpga_top.sb_2__0_.mem_left_track_7.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -2752,7 +2752,7 @@
|
|||
</bit>
|
||||
<bit id="999" value="0" path="fpga_top.sb_2__0_.mem_left_track_3.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="998" value="0" path="fpga_top.sb_2__0_.mem_left_track_3.mem_out[0]">
|
||||
<bit id="998" value="1" path="fpga_top.sb_2__0_.mem_left_track_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="997" value="0" path="fpga_top.sb_2__0_.mem_left_track_1.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -3894,9 +3894,9 @@
|
|||
</bit>
|
||||
<bit id="428" value="0" path="fpga_top.sb_0__0_.mem_right_track_4.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="427" value="0" path="fpga_top.sb_0__0_.mem_right_track_2.mem_out[1]">
|
||||
<bit id="427" value="1" path="fpga_top.sb_0__0_.mem_right_track_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="426" value="0" path="fpga_top.sb_0__0_.mem_right_track_2.mem_out[0]">
|
||||
<bit id="426" value="1" path="fpga_top.sb_0__0_.mem_right_track_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="425" value="0" path="fpga_top.sb_0__0_.mem_right_track_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -4086,17 +4086,17 @@
|
|||
</bit>
|
||||
<bit id="332" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="331" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[7]">
|
||||
<bit id="331" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="330" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="329" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[5]">
|
||||
<bit id="329" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="328" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="327" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="326" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[2]">
|
||||
<bit id="326" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="325" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -4426,9 +4426,9 @@
|
|||
</bit>
|
||||
<bit id="162" value="0" path="fpga_top.sb_1__2_.mem_bottom_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="161" value="1" path="fpga_top.sb_1__2_.mem_bottom_track_7.mem_out[1]">
|
||||
<bit id="161" value="0" path="fpga_top.sb_1__2_.mem_bottom_track_7.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="160" value="1" path="fpga_top.sb_1__2_.mem_bottom_track_7.mem_out[0]">
|
||||
<bit id="160" value="0" path="fpga_top.sb_1__2_.mem_bottom_track_7.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="159" value="0" path="fpga_top.sb_1__2_.mem_bottom_track_5.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -4458,9 +4458,9 @@
|
|||
</bit>
|
||||
<bit id="146" value="0" path="fpga_top.sb_1__2_.mem_bottom_track_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="145" value="0" path="fpga_top.sb_1__2_.mem_right_track_16.mem_out[5]">
|
||||
<bit id="145" value="1" path="fpga_top.sb_1__2_.mem_right_track_16.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="144" value="1" path="fpga_top.sb_1__2_.mem_right_track_16.mem_out[4]">
|
||||
<bit id="144" value="0" path="fpga_top.sb_1__2_.mem_right_track_16.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="143" value="0" path="fpga_top.sb_1__2_.mem_right_track_16.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -4470,13 +4470,13 @@
|
|||
</bit>
|
||||
<bit id="140" value="0" path="fpga_top.sb_1__2_.mem_right_track_16.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="139" value="0" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[7]">
|
||||
<bit id="139" value="1" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="138" value="0" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="137" value="0" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="136" value="1" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[4]">
|
||||
<bit id="136" value="0" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="135" value="0" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -4484,7 +4484,7 @@
|
|||
</bit>
|
||||
<bit id="133" value="0" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="132" value="1" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[0]">
|
||||
<bit id="132" value="0" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="131" value="1" path="fpga_top.sb_1__2_.mem_right_track_0.mem_out[7]">
|
||||
</bit>
|
||||
|
|
@ -4510,7 +4510,7 @@
|
|||
</bit>
|
||||
<bit id="120" value="1" path="fpga_top.grid_io_top_2__3_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="119" value="0" path="fpga_top.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
<bit id="119" value="1" path="fpga_top.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="118" value="1" path="fpga_top.grid_io_top_2__3_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -4566,13 +4566,13 @@
|
|||
</bit>
|
||||
<bit id="92" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_4.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="91" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[5]">
|
||||
<bit id="91" value="1" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="90" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="89" value="1" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[3]">
|
||||
<bit id="89" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="88" value="1" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[2]">
|
||||
<bit id="88" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="87" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -4626,7 +4626,7 @@
|
|||
</bit>
|
||||
<bit id="62" value="0" path="fpga_top.sb_2__2_.mem_left_track_11.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="61" value="1" path="fpga_top.sb_2__2_.mem_left_track_9.mem_out[1]">
|
||||
<bit id="61" value="0" path="fpga_top.sb_2__2_.mem_left_track_9.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="60" value="0" path="fpga_top.sb_2__2_.mem_left_track_9.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -4670,7 +4670,7 @@
|
|||
</bit>
|
||||
<bit id="40" value="0" path="fpga_top.sb_2__2_.mem_bottom_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="39" value="1" path="fpga_top.sb_2__2_.mem_bottom_track_7.mem_out[1]">
|
||||
<bit id="39" value="0" path="fpga_top.sb_2__2_.mem_bottom_track_7.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="38" value="0" path="fpga_top.sb_2__2_.mem_bottom_track_7.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -4728,7 +4728,7 @@
|
|||
</bit>
|
||||
<bit id="11" value="1" path="fpga_top.grid_io_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="10" value="1" path="fpga_top.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
<bit id="10" value="0" path="fpga_top.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="9" value="1" path="fpga_top.grid_io_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
</bit>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -14,7 +14,7 @@ set_units -time s
|
|||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 1.11238041e-09 -waveform {0 5.56190205e-10} [get_ports {clk[0]}]
|
||||
create_clock -name clk[0] -period 8.970345577e-10 -waveform {0 4.485172789e-10} [get_ports {clk[0]}]
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
-->
|
||||
|
||||
<io_mapping>
|
||||
<io name="gfpga_pad_GPIO_PAD[12:12]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[9:9]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[11:11]" net="c" dir="output"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[39:39]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[48:48]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[34:34]" net="c" dir="output"/>
|
||||
</io_mapping>
|
||||
|
|
|
|||
Loading…
Reference in New Issue