[test] update golden outputs for device4x4
This commit is contained in:
tangxifan
parent
5f74367c2e
commit
a88bc2d4de
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@ -50,7 +50,7 @@ module and2_top_formal_verification_random_tb;
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initial begin
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clk[0] <= 1'b0;
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while(1) begin
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#0.5422864556
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#0.6573184729
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clk[0] <= !clk[0];
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end
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end
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@ -109,7 +109,7 @@ initial begin
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$timeformat(-9, 2, "ns", 20);
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$display("Simulation start");
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// ----- Can be changed by the user for his/her need -------
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#7.592010975
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#9.202458382
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if(nb_error == 0) begin
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$display("Simulation Succeed");
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end else begin
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File diff suppressed because it is too large
Load Diff
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@ -42,14 +42,14 @@ wire [0:0] clk_fm;
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// ----- End Connect Global ports of FPGA top module -----
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// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
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// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[13] -----
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assign gfpga_pad_GPIO_PAD_fm[13] = a[0];
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// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[38] -----
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assign gfpga_pad_GPIO_PAD_fm[38] = a[0];
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// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] -----
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assign gfpga_pad_GPIO_PAD_fm[12] = b[0];
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// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[58] -----
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assign gfpga_pad_GPIO_PAD_fm[58] = b[0];
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// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[10] -----
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assign c[0] = gfpga_pad_GPIO_PAD_fm[10];
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// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[17] -----
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assign c[0] = gfpga_pad_GPIO_PAD_fm[17];
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// ----- Wire unused FPGA I/Os to constants -----
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assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
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@ -62,11 +62,13 @@ wire [0:0] clk_fm;
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assign gfpga_pad_GPIO_PAD_fm[7] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[17] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[18] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[19] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[20] = 1'b0;
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@ -87,7 +89,6 @@ wire [0:0] clk_fm;
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assign gfpga_pad_GPIO_PAD_fm[35] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[36] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[37] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[38] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[39] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[40] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[41] = 1'b0;
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@ -107,7 +108,6 @@ wire [0:0] clk_fm;
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assign gfpga_pad_GPIO_PAD_fm[55] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[56] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[57] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[58] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[59] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[60] = 1'b0;
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assign gfpga_pad_GPIO_PAD_fm[61] = 1'b0;
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@ -529,10 +529,10 @@ initial begin
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000;
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111;
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01;
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10;
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}};
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@ -557,14 +557,14 @@ initial begin
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b1101;
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b0010;
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_3__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
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force U0_formal_verification.grid_clb_3__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
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force U0_formal_verification.grid_clb_3__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
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@ -865,10 +865,10 @@ initial begin
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000;
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111;
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01;
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10;
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}};
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@ -893,14 +893,14 @@ initial begin
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b1110;
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b0001;
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0001;
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force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1110;
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force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
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force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
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force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
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@ -969,8 +969,8 @@ initial begin
|
|||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -983,8 +983,8 @@ initial begin
|
|||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -1241,8 +1241,8 @@ initial begin
|
|||
force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:3] = 4'b0011;
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:3] = 4'b1100;
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -1337,8 +1337,8 @@ initial begin
|
|||
force U0_formal_verification.sb_0__4_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_10.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_14.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1409,8 +1409,8 @@ initial begin
|
|||
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_out[0:3] = 4'b0111;
|
||||
force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_outb[0:3] = 4'b1000;
|
||||
force U0_formal_verification.sb_1__2_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_1__2_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__2_.mem_top_track_16.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -1457,8 +1457,8 @@ initial begin
|
|||
force U0_formal_verification.sb_1__3_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__3_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_1__3_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_out[0:3] = 4'b0011;
|
||||
force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_outb[0:3] = 4'b1100;
|
||||
force U0_formal_verification.sb_1__4_.mem_right_track_8.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_1__4_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__4_.mem_right_track_16.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -1531,8 +1531,8 @@ initial begin
|
|||
force U0_formal_verification.sb_2__1_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_out[0:3] = 4'b0111;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_outb[0:3] = 4'b1000;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -1593,8 +1593,8 @@ initial begin
|
|||
force U0_formal_verification.sb_2__4_.mem_right_track_16.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_1.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1613,10 +1613,10 @@ initial begin
|
|||
force U0_formal_verification.sb_2__4_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_out[0:3] = 4'b0010;
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_outb[0:3] = 4'b1101;
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_out[0:3] = 4'b0010;
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_outb[0:3] = 4'b1101;
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1641,8 +1641,8 @@ initial begin
|
|||
force U0_formal_verification.sb_3__0_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_out[0:3] = 4'b0111;
|
||||
force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_outb[0:3] = 4'b1000;
|
||||
force U0_formal_verification.sb_3__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_3__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -1683,8 +1683,8 @@ initial begin
|
|||
force U0_formal_verification.sb_3__2_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__2_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_3__2_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_out[0:3] = 4'b0101;
|
||||
force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_outb[0:3] = 4'b1010;
|
||||
force U0_formal_verification.sb_3__2_.mem_left_track_9.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_3__2_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -1751,8 +1751,8 @@ initial begin
|
|||
force U0_formal_verification.sb_4__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1795,8 +1795,8 @@ initial begin
|
|||
force U0_formal_verification.sb_4__1_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_1.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1833,8 +1833,8 @@ initial begin
|
|||
force U0_formal_verification.sb_4__2_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_13.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1855,8 +1855,8 @@ initial begin
|
|||
force U0_formal_verification.sb_4__3_.mem_bottom_track_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_bottom_track_9.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_4__3_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_out[0:3] = 4'b0101;
|
||||
force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_outb[0:3] = 4'b1010;
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_1.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1867,8 +1867,8 @@ initial begin
|
|||
force U0_formal_verification.sb_4__3_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_13.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_13.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_15.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1889,8 +1889,8 @@ initial begin
|
|||
force U0_formal_verification.sb_4__4_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_15.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -2055,8 +2055,8 @@ initial begin
|
|||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_out[0:2] = 3'b001;
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_outb[0:2] = 3'b110;
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_3.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_4.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
@ -2067,10 +2067,10 @@ initial begin
|
|||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_out[0:2] = 3'b010;
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_outb[0:2] = 3'b101;
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_out[0:2] = 3'b011;
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_outb[0:2] = 3'b100;
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_3__0_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
@ -2133,8 +2133,8 @@ initial begin
|
|||
force U0_formal_verification.cbx_3__3_.mem_top_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
@ -2209,8 +2209,8 @@ initial begin
|
|||
force U0_formal_verification.cbx_4__3_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_4__3_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_4__3_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
@ -2415,8 +2415,8 @@ initial begin
|
|||
force U0_formal_verification.cby_3__2_.mem_right_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cby_3__3_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_3__3_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cby_3__3_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_3__3_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_3__3_.mem_right_ipin_1.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
|
|||
|
|
@ -213,10 +213,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -225,10 +222,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -277,25 +270,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -830,6 +804,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -853,6 +828,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -863,7 +840,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -885,6 +864,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -897,6 +877,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -945,6 +928,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -955,9 +939,13 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1069,6 +1057,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1244,6 +1234,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1271,7 +1263,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1729,6 +1723,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2111,9 +2108,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2365,6 +2359,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2565,6 +2562,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2819,6 +2817,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3625,8 +3625,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
|
|
@ -3805,7 +3805,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3899,8 +3899,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
|
|
@ -3908,16 +3908,13 @@
|
|||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3934,7 +3931,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3944,11 +3940,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3971,8 +3965,14 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3993,11 +3993,8 @@
|
|||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -4024,6 +4021,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -4133,8 +4133,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
|
|||
|
|
@ -430,13 +430,13 @@
|
|||
</bit>
|
||||
<bit id="3998" value="0" path="fpga_top.sb_1__3_.mem_top_track_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3997" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
|
||||
<bit id="3997" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3996" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3995" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]">
|
||||
<bit id="3995" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3994" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
|
||||
<bit id="3994" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3993" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -454,13 +454,13 @@
|
|||
</bit>
|
||||
<bit id="3986" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3985" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
|
||||
<bit id="3985" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3984" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
<bit id="3984" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3983" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
|
||||
<bit id="3983" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3982" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
|
||||
<bit id="3982" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3981" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -558,7 +558,7 @@
|
|||
</bit>
|
||||
<bit id="3934" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3933" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
<bit id="3933" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3932" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -580,19 +580,19 @@
|
|||
</bit>
|
||||
<bit id="3923" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="3922" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
|
||||
<bit id="3922" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="3921" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="3920" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
|
||||
<bit id="3920" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="3919" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3918" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
|
||||
<bit id="3918" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3917" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3916" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
|
||||
<bit id="3916" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3915" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -1612,7 +1612,7 @@
|
|||
</bit>
|
||||
<bit id="3407" value="0" path="fpga_top.cby_4__4_.mem_left_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3406" value="0" path="fpga_top.cbx_4__3_.mem_top_ipin_2.mem_out[1]">
|
||||
<bit id="3406" value="1" path="fpga_top.cbx_4__3_.mem_top_ipin_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3405" value="0" path="fpga_top.cbx_4__3_.mem_top_ipin_2.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -1660,9 +1660,9 @@
|
|||
</bit>
|
||||
<bit id="3383" value="0" path="fpga_top.sb_4__3_.mem_left_track_13.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3382" value="0" path="fpga_top.sb_4__3_.mem_left_track_11.mem_out[1]">
|
||||
<bit id="3382" value="1" path="fpga_top.sb_4__3_.mem_left_track_11.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3381" value="0" path="fpga_top.sb_4__3_.mem_left_track_11.mem_out[0]">
|
||||
<bit id="3381" value="1" path="fpga_top.sb_4__3_.mem_left_track_11.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3380" value="0" path="fpga_top.sb_4__3_.mem_left_track_9.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -1684,11 +1684,11 @@
|
|||
</bit>
|
||||
<bit id="3371" value="0" path="fpga_top.sb_4__3_.mem_left_track_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3370" value="0" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[3]">
|
||||
<bit id="3370" value="1" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3369" value="0" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3368" value="0" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[1]">
|
||||
<bit id="3368" value="1" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3367" value="0" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -1732,7 +1732,7 @@
|
|||
</bit>
|
||||
<bit id="3347" value="0" path="fpga_top.sb_4__3_.mem_top_track_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3346" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
|
||||
<bit id="3346" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3345" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -1758,11 +1758,11 @@
|
|||
</bit>
|
||||
<bit id="3334" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3333" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
<bit id="3333" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3332" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
|
||||
<bit id="3332" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3331" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
|
||||
<bit id="3331" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3330" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -1860,7 +1860,7 @@
|
|||
</bit>
|
||||
<bit id="3283" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3282" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
<bit id="3282" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3281" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -1882,19 +1882,19 @@
|
|||
</bit>
|
||||
<bit id="3272" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="3271" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
|
||||
<bit id="3271" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="3270" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="3269" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
|
||||
<bit id="3269" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="3268" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3267" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
|
||||
<bit id="3267" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3266" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3265" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
|
||||
<bit id="3265" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3264" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -2118,9 +2118,9 @@
|
|||
</bit>
|
||||
<bit id="3154" value="0" path="fpga_top.sb_4__2_.mem_left_track_11.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3153" value="0" path="fpga_top.sb_4__2_.mem_left_track_9.mem_out[1]">
|
||||
<bit id="3153" value="1" path="fpga_top.sb_4__2_.mem_left_track_9.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3152" value="0" path="fpga_top.sb_4__2_.mem_left_track_9.mem_out[0]">
|
||||
<bit id="3152" value="1" path="fpga_top.sb_4__2_.mem_left_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3151" value="0" path="fpga_top.sb_4__2_.mem_left_track_7.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -2472,9 +2472,9 @@
|
|||
</bit>
|
||||
<bit id="2977" value="0" path="fpga_top.cby_3__3_.mem_right_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="2976" value="0" path="fpga_top.cby_3__3_.mem_left_ipin_1.mem_out[1]">
|
||||
<bit id="2976" value="1" path="fpga_top.cby_3__3_.mem_left_ipin_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="2975" value="0" path="fpga_top.cby_3__3_.mem_left_ipin_1.mem_out[0]">
|
||||
<bit id="2975" value="1" path="fpga_top.cby_3__3_.mem_left_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="2974" value="0" path="fpga_top.cby_3__3_.mem_left_ipin_0.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -2530,11 +2530,11 @@
|
|||
</bit>
|
||||
<bit id="2948" value="0" path="fpga_top.sb_3__2_.mem_left_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="2947" value="0" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[3]">
|
||||
<bit id="2947" value="1" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="2946" value="0" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="2945" value="0" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[1]">
|
||||
<bit id="2945" value="1" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="2944" value="0" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -3450,11 +3450,11 @@
|
|||
</bit>
|
||||
<bit id="2488" value="0" path="fpga_top.sb_1__2_.mem_top_track_8.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="2487" value="0" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[3]">
|
||||
<bit id="2487" value="1" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="2486" value="0" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[2]">
|
||||
<bit id="2486" value="1" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="2485" value="0" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[1]">
|
||||
<bit id="2485" value="1" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="2484" value="0" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -4226,11 +4226,11 @@
|
|||
</bit>
|
||||
<bit id="2100" value="0" path="fpga_top.sb_2__1_.mem_left_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="2099" value="1" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[3]">
|
||||
<bit id="2099" value="0" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="2098" value="1" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[2]">
|
||||
<bit id="2098" value="0" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="2097" value="1" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[1]">
|
||||
<bit id="2097" value="0" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="2096" value="0" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -4722,11 +4722,11 @@
|
|||
</bit>
|
||||
<bit id="1852" value="0" path="fpga_top.sb_3__1_.mem_top_track_8.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1851" value="0" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[3]">
|
||||
<bit id="1851" value="1" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1850" value="0" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[2]">
|
||||
<bit id="1850" value="1" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1849" value="0" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[1]">
|
||||
<bit id="1849" value="1" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1848" value="0" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -5128,7 +5128,7 @@
|
|||
</bit>
|
||||
<bit id="1649" value="0" path="fpga_top.sb_4__1_.mem_left_track_5.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1648" value="0" path="fpga_top.sb_4__1_.mem_left_track_3.mem_out[1]">
|
||||
<bit id="1648" value="1" path="fpga_top.sb_4__1_.mem_left_track_3.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1647" value="0" path="fpga_top.sb_4__1_.mem_left_track_3.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -5638,9 +5638,9 @@
|
|||
</bit>
|
||||
<bit id="1394" value="0" path="fpga_top.sb_4__0_.mem_top_track_8.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1393" value="0" path="fpga_top.sb_4__0_.mem_top_track_6.mem_out[1]">
|
||||
<bit id="1393" value="1" path="fpga_top.sb_4__0_.mem_top_track_6.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1392" value="0" path="fpga_top.sb_4__0_.mem_top_track_6.mem_out[0]">
|
||||
<bit id="1392" value="1" path="fpga_top.sb_4__0_.mem_top_track_6.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1391" value="0" path="fpga_top.sb_4__0_.mem_top_track_4.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7254,9 +7254,9 @@
|
|||
</bit>
|
||||
<bit id="586" value="0" path="fpga_top.sb_0__1_.mem_top_track_8.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="585" value="1" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[3]">
|
||||
<bit id="585" value="0" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="584" value="1" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[2]">
|
||||
<bit id="584" value="0" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="583" value="0" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7614,7 +7614,7 @@
|
|||
</bit>
|
||||
<bit id="406" value="0" path="fpga_top.sb_0__4_.mem_right_track_14.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="405" value="1" path="fpga_top.sb_0__4_.mem_right_track_12.mem_out[1]">
|
||||
<bit id="405" value="0" path="fpga_top.sb_0__4_.mem_right_track_12.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="404" value="0" path="fpga_top.sb_0__4_.mem_right_track_12.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -7802,9 +7802,9 @@
|
|||
</bit>
|
||||
<bit id="312" value="0" path="fpga_top.sb_1__4_.mem_right_track_8.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="311" value="0" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[3]">
|
||||
<bit id="311" value="1" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="310" value="0" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[2]">
|
||||
<bit id="310" value="1" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="309" value="0" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7820,7 +7820,7 @@
|
|||
</bit>
|
||||
<bit id="303" value="1" path="fpga_top.grid_io_top_2__5_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="302" value="0" path="fpga_top.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
<bit id="302" value="1" path="fpga_top.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="301" value="1" path="fpga_top.grid_io_top_2__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -7830,15 +7830,15 @@
|
|||
</bit>
|
||||
<bit id="298" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="297" value="1" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[2]">
|
||||
<bit id="297" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="296" value="1" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[1]">
|
||||
<bit id="296" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="295" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="294" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="293" value="1" path="fpga_top.cbx_2__4_.mem_top_ipin_0.mem_out[1]">
|
||||
<bit id="293" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="292" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -7872,7 +7872,7 @@
|
|||
</bit>
|
||||
<bit id="277" value="0" path="fpga_top.cbx_2__4_.mem_bottom_ipin_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="276" value="1" path="fpga_top.cbx_2__4_.mem_bottom_ipin_2.mem_out[2]">
|
||||
<bit id="276" value="0" path="fpga_top.cbx_2__4_.mem_bottom_ipin_2.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="275" value="0" path="fpga_top.cbx_2__4_.mem_bottom_ipin_2.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7892,7 +7892,7 @@
|
|||
</bit>
|
||||
<bit id="267" value="0" path="fpga_top.sb_2__4_.mem_left_track_17.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="266" value="1" path="fpga_top.sb_2__4_.mem_left_track_17.mem_out[2]">
|
||||
<bit id="266" value="0" path="fpga_top.sb_2__4_.mem_left_track_17.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="265" value="0" path="fpga_top.sb_2__4_.mem_left_track_17.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7900,7 +7900,7 @@
|
|||
</bit>
|
||||
<bit id="263" value="0" path="fpga_top.sb_2__4_.mem_left_track_9.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="262" value="1" path="fpga_top.sb_2__4_.mem_left_track_9.mem_out[2]">
|
||||
<bit id="262" value="0" path="fpga_top.sb_2__4_.mem_left_track_9.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="261" value="0" path="fpga_top.sb_2__4_.mem_left_track_9.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7946,9 +7946,9 @@
|
|||
</bit>
|
||||
<bit id="240" value="0" path="fpga_top.sb_2__4_.mem_bottom_track_5.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="239" value="1" path="fpga_top.sb_2__4_.mem_bottom_track_3.mem_out[1]">
|
||||
<bit id="239" value="0" path="fpga_top.sb_2__4_.mem_bottom_track_3.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="238" value="1" path="fpga_top.sb_2__4_.mem_bottom_track_3.mem_out[0]">
|
||||
<bit id="238" value="0" path="fpga_top.sb_2__4_.mem_bottom_track_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="237" value="0" path="fpga_top.sb_2__4_.mem_bottom_track_1.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7990,7 +7990,7 @@
|
|||
</bit>
|
||||
<bit id="218" value="1" path="fpga_top.grid_io_top_3__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="217" value="1" path="fpga_top.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
<bit id="217" value="0" path="fpga_top.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="216" value="1" path="fpga_top.grid_io_top_3__5_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -8046,11 +8046,11 @@
|
|||
</bit>
|
||||
<bit id="190" value="0" path="fpga_top.cbx_3__4_.mem_bottom_ipin_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="189" value="0" path="fpga_top.cbx_3__4_.mem_bottom_ipin_1.mem_out[2]">
|
||||
<bit id="189" value="1" path="fpga_top.cbx_3__4_.mem_bottom_ipin_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="188" value="0" path="fpga_top.cbx_3__4_.mem_bottom_ipin_1.mem_out[1]">
|
||||
<bit id="188" value="1" path="fpga_top.cbx_3__4_.mem_bottom_ipin_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="187" value="0" path="fpga_top.cbx_3__4_.mem_bottom_ipin_1.mem_out[0]">
|
||||
<bit id="187" value="1" path="fpga_top.cbx_3__4_.mem_bottom_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="186" value="0" path="fpga_top.cbx_3__4_.mem_bottom_ipin_0.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -8270,9 +8270,9 @@
|
|||
</bit>
|
||||
<bit id="78" value="0" path="fpga_top.sb_4__4_.mem_bottom_track_15.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="77" value="0" path="fpga_top.sb_4__4_.mem_bottom_track_13.mem_out[1]">
|
||||
<bit id="77" value="1" path="fpga_top.sb_4__4_.mem_bottom_track_13.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="76" value="0" path="fpga_top.sb_4__4_.mem_bottom_track_13.mem_out[0]">
|
||||
<bit id="76" value="1" path="fpga_top.sb_4__4_.mem_bottom_track_13.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="75" value="0" path="fpga_top.sb_4__4_.mem_bottom_track_11.mem_out[1]">
|
||||
</bit>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -14,7 +14,7 @@ set_units -time s
|
|||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 1.084572876e-09 -waveform {0 5.42286438e-10} [get_ports {clk[0]}]
|
||||
create_clock -name clk[0] -period 1.314636955e-09 -waveform {0 6.573184774e-10} [get_ports {clk[0]}]
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
-->
|
||||
|
||||
<io_mapping>
|
||||
<io name="gfpga_pad_GPIO_PAD[13:13]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[12:12]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[10:10]" net="c" dir="output"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[38:38]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[58:58]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[17:17]" net="c" dir="output"/>
|
||||
</io_mapping>
|
||||
|
|
|
|||
Loading…
Reference in New Issue