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[test] reworked test case on pcf2place

This commit is contained in:
tangxifan 2022-07-28 11:51:56 -07:00
parent c1256ae818
commit ec31e124b7
4 changed files with 24 additions and 34 deletions
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4
openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga
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@ -1,5 +1,5 @@
# Run constrain_pin_location
constrain_pin_location --pcf ${AND2_PIN_CONSTRAIN_FILE} --blif ${VPR_TESTBENCH_BLIF} --pinmap_xml ${AND2_PIN_MAP_XML_FILE} --csv_file ${AND2_PIN_MAP_CSV_FILE} --output ${OPENFPGA_VPR_FIX_PINS_FILE}
# Convert .pcf to a .place file that VPR can accept
pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE}
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml

18
openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_map.xml Normal file
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@ -0,0 +1,18 @@
<io_coordinates>
<io pad="gfpga_pad_IO_A2F[0]" x="1" y="2" z="0"/>
<io pad="gfpga_pad_IO_F2A[0]" x="1" y="2" z="1"/>
<io pad="gfpga_pad_IO_A2F[1]" x="1" y="2" z="2"/>
<io pad="gfpga_pad_IO_F2A[1]" x="1" y="2" z="3"/>
<io pad="gfpga_pad_IO_A2F[2]" x="1" y="2" z="4"/>
<io pad="gfpga_pad_IO_F2A[2]" x="1" y="2" z="5"/>
<io pad="gfpga_pad_IO_A2F[3]" x="1" y="2" z="6"/>
<io pad="gfpga_pad_IO_F2A[3]" x="1" y="2" z="7"/>
<io pad="gfpga_pad_IO_A2F[4]" x="2" y="1" z="0"/>
<io pad="gfpga_pad_IO_F2A[4]" x="2" y="1" z="1"/>
<io pad="gfpga_pad_IO_A2F[5]" x="2" y="1" z="2"/>
<io pad="gfpga_pad_IO_F2A[5]" x="2" y="1" z="3"/>
<io pad="gfpga_pad_IO_A2F[6]" x="2" y="1" z="4"/>
<io pad="gfpga_pad_IO_F2A[6]" x="2" y="1" z="5"/>
<io pad="gfpga_pad_IO_A2F[7]" x="2" y="1" z="6"/>
<io pad="gfpga_pad_IO_F2A[7]" x="2" y="1" z="7"/>
</io_coordinates>

28
openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.xml
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@ -1,28 +0,0 @@
<?xml version="1.0" encoding="utf-8"?>
<!--
XML file specification is primarily to define the mapping of the interface cell ports defined
in vpr_arch xml, to the EFPGA IO interface port names. This mapping is required by OpenFPGA
alongwith architecture definition file i.e. vpr_arch xml file. OpenFPGA will process this
file and use this information for IO placement and then later on use this to map it with the
user-defined pin-mapping file.
-->
<DEVICE name= "k4_N4_tileable_40nm" family="k4n4" width="6" height="6" z="8">
<IO>
<TOP_IO y="5">
<CELL port_name="output" mapped_name="gfpga_pad_IO_F2A[0:31]" startx="1" endx="4"/>
<CELL port_name="input" mapped_name="gfpga_pad_IO_A2F[0:31]" startx="1" endx="4"/>
</TOP_IO>
<RIGHT_IO x="5">
<CELL port_name="output" mapped_name="gfpga_pad_IO_F2A[32:63]" starty="4" endy="1"/>
<CELL port_name="input" mapped_name="gfpga_pad_IO_A2F[32:63]" starty="4" endy="1"/>
</RIGHT_IO>
<BOTTOM_IO y="0">
<CELL port_name="output" mapped_name="gfpga_pad_IO_F2A[64:95]" startx="4" endx="1"/>
<CELL port_name="input" mapped_name="gfpga_pad_IO_A2F[64:95]" startx="4" endx="1"/>
</BOTTOM_IO>
<LEFT_IO x="0">
<CELL port_name="output" mapped_name="gfpga_pad_IO_F2A[96:127]" starty="1" endy="4"/>
<CELL port_name="input" mapped_name="gfpga_pad_IO_A2F[96:127]" starty="1" endy="4"/>
</LEFT_IO>
</IO>
</DEVICE>

8
openfpga_flow/tasks/basic_tests/constrain_pin_location/config/task.conf
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@ -21,10 +21,10 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=4x4
openfpga_vpr_route_chan_width=20
and2_pin_constrain_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf
and2_pin_map_xml_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.xml
and2_pin_map_csv_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv
openfpga_vpr_fix_pins_file=./and2_constrain_pin.place
openfpga_pcf=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf
openfpga_io_map_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_map.xml
openfpga_pin_table=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv
openfpga_vpr_fix_pins_file=and2_fix_pins.place
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml