[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
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@ -18,7 +18,7 @@ run-task fpga_bitstream/generate_bitstream/ql_memory_bank_shift_register/device_
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echo -e "Testing bitstream generation for an 96x96 FPGA device";
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run-task fpga_bitstream/generate_bitstream/configuration_chain/device_96x96 $@
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run-task fpga_bitstream/generate_bitstream/ql_memory_bank_shift_register/device_96x96 $@
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run-task fpga_bitstream/generate_bitstream/ql_memory_bank_shift_register/device_72x72 $@
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echo -e "Testing loading architecture bitstream from an external file";
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run-task fpga_bitstream/load_external_architecture_bitstream $@
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@ -21,7 +21,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
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openfpga_vpr_route_chan_width=100
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openfpga_vpr_device_layout=96x96
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openfpga_vpr_device_layout=72x72
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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@ -91,6 +91,13 @@
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</fixed_layout>
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<fixed_layout name="72x72" width="74" height="74">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</fixed_layout>
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<fixed_layout name="96x96" width="98" height="98">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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