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[engine] now frame view will not build nets for configuration bus

This commit is contained in:
tangxifan 2022-09-01 20:02:00 -07:00
parent 001367ea41
commit d3f08a893c
1 changed files with 8 additions and 6 deletions
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14
openfpga/src/fabric/build_top_module.cpp
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@ -428,12 +428,14 @@ int build_top_module(ModuleManager& module_manager,
/* Add module nets to connect memory cells inside
* This is a one-shot addition that covers all the memory modules in this pb module!
*/
if (0 < module_manager.configurable_children(top_module).size()) {
add_top_module_nets_memory_config_bus(module_manager, decoder_lib, blwl_sr_banks,
top_module,
circuit_lib,
config_protocol, circuit_lib.design_tech_type(sram_model),
top_module_num_config_bits);
if (false == frame_view) {
if (0 < module_manager.configurable_children(top_module).size()) {
add_top_module_nets_memory_config_bus(module_manager, decoder_lib, blwl_sr_banks,
top_module,
circuit_lib,
config_protocol, circuit_lib.design_tech_type(sram_model),
top_module_num_config_bits);
}
}
/* Add global ports to the top module: