From d3f08a893ce4722f499526e46dd8b18611fc2019 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Sep 2022 20:02:00 -0700 Subject: [PATCH] [engine] now frame view will not build nets for configuration bus --- openfpga/src/fabric/build_top_module.cpp | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 2aad3f1f4..76da64d9f 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -428,12 +428,14 @@ int build_top_module(ModuleManager& module_manager, /* Add module nets to connect memory cells inside * This is a one-shot addition that covers all the memory modules in this pb module! */ - if (0 < module_manager.configurable_children(top_module).size()) { - add_top_module_nets_memory_config_bus(module_manager, decoder_lib, blwl_sr_banks, - top_module, - circuit_lib, - config_protocol, circuit_lib.design_tech_type(sram_model), - top_module_num_config_bits); + if (false == frame_view) { + if (0 < module_manager.configurable_children(top_module).size()) { + add_top_module_nets_memory_config_bus(module_manager, decoder_lib, blwl_sr_banks, + top_module, + circuit_lib, + config_protocol, circuit_lib.design_tech_type(sram_model), + top_module_num_config_bits); + } } /* Add global ports to the top module: