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[arch] syntax

This commit is contained in:
tangxifan 2022-05-09 17:13:57 +08:00
parent effa9e0f41
commit 9f56e61342
1 changed files with 13 additions and 13 deletions
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26
openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml
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@ -70,6 +70,17 @@
<port name="Q" clock="C"/>
</output_ports>
</model>
<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
<model name="dffnr">
<input_ports>
<port name="D" clock="CN"/>
<port name="R" clock="CN"/>
<port name="CN" is_clock="1"/>
</input_ports>
<output_ports>
<port name="Q" clock="CN"/>
</output_ports>
</model>
<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
<model name="dffrn">
<input_ports>
@ -82,17 +93,6 @@
</output_ports>
</model>
<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
<model name="dffnrn">
<input_ports>
<port name="D" clock="CN"/>
<port name="R" clock="CN"/>
<port name="CN" is_clock="1"/>
</input_ports>
<output_ports>
<port name="Q" clock="CN"/>
</output_ports>
</model>
<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
<model name="dffnrn">
<input_ports>
<port name="D" clock="CN"/>
@ -447,7 +447,7 @@
</pb_type>
<interconnect>
<direct name="direct1" input="ff.D" output="dffn.D"/>
<direct name="direct2" input="ff.CN" output="dffn.CN"/>
<direct name="direct2" input="ff.C" output="dffn.CN"/>
<direct name="direct3" input="dffn.Q" output="ff.Q"/>
</interconnect>
</mode>
@ -624,7 +624,7 @@
</pb_type>
<interconnect>
<direct name="direct1" input="ff.D" output="dffn.D"/>
<direct name="direct2" input="ff.CN" output="dffn.CN"/>
<direct name="direct2" input="ff.C" output="dffn.CN"/>
<direct name="direct3" input="dffn.Q" output="ff.Q"/>
</interconnect>
</mode>