From 9f56e613426954217671163dce55e61ca14594ff Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 9 May 2022 17:13:57 +0800
Subject: [PATCH] [arch] syntax

---
 .../k4_frac_N4_tileable_fracff2edge_40nm.xml  | 26 +++++++++----------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml
index 43081040d..21d08c961 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml
@@ -70,6 +70,17 @@
         <port name="Q" clock="C"/>
       </output_ports>
     </model>
+    <!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
+    <model name="dffnr">
+      <input_ports>
+        <port name="D" clock="CN"/>
+        <port name="R" clock="CN"/>
+        <port name="CN" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="CN"/>
+      </output_ports>
+    </model>
    <!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
     <model name="dffrn">
       <input_ports>
@@ -82,17 +93,6 @@
       </output_ports>
     </model>
     <!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
-    <model name="dffnrn">
-      <input_ports>
-        <port name="D" clock="CN"/>
-        <port name="R" clock="CN"/>
-        <port name="CN" is_clock="1"/>
-      </input_ports>
-      <output_ports>
-        <port name="Q" clock="CN"/>
-      </output_ports>
-    </model>
-   <!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
     <model name="dffnrn">
       <input_ports>
         <port name="D" clock="CN"/>
@@ -447,7 +447,7 @@
                   </pb_type> 
                   <interconnect>
                     <direct name="direct1" input="ff.D" output="dffn.D"/>
-                    <direct name="direct2" input="ff.CN" output="dffn.CN"/>
+                    <direct name="direct2" input="ff.C" output="dffn.CN"/>
                     <direct name="direct3" input="dffn.Q" output="ff.Q"/>
                   </interconnect>
                 </mode>
@@ -624,7 +624,7 @@
                 </pb_type> 
                 <interconnect>
                   <direct name="direct1" input="ff.D" output="dffn.D"/>
-                  <direct name="direct2" input="ff.CN" output="dffn.CN"/>
+                  <direct name="direct2" input="ff.C" output="dffn.CN"/>
                   <direct name="direct3" input="dffn.Q" output="ff.Q"/>
                 </interconnect>
               </mode>