[test] add 'write_fabric_io_info' command to test cases

openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga

@@ -24,6 +24,10 @@ build_fabric --compress_routing #--verbose
 # This is used by hierarchical PnR flows
 write_fabric_hierarchy --file ./fabric_hierarchy.txt
 
+# Write the fabric I/O attributes to a file
+# This is used by pin constraint files
+write_fabric_io --file ./fabric_io_location.xml --verbose
+
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
 write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose

openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga

@@ -32,6 +32,10 @@ build_fabric --compress_routing #--verbose
 # This is used by hierarchical PnR flows
 write_fabric_hierarchy --file ./fabric_hierarchy.txt
 
+# Write the fabric I/O attributes to a file
+# This is used by pin constraint files
+write_fabric_io --file ./fabric_io_location.xml --verbose --no_time_stamp
+
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
 # Strongly recommend it is done after all the fix-up have been applied

openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_no_time_stamp_example_script.openfpga

@@ -30,6 +30,10 @@ build_fabric --compress_routing #--verbose
 # This is used by hierarchical PnR flows
 write_fabric_hierarchy --file ./fabric_hierarchy.txt
 
+# Write the fabric I/O attributes to a file
+# This is used by pin constraint files
+write_fabric_io --file ./fabric_io_location.xml --verbose --no_time_stamp
+
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
 # Strongly recommend it is done after all the fix-up have been applied