[test] now regression test script supports remove all run dir through command-line options
This commit is contained in:
tangxifan
parent
751d87b8e3
commit
0dc7caf3b7
|
|
@ -65,6 +65,10 @@ clean-run () {
|
|||
rm -rf ./openfpga_flow/**/run???
|
||||
}
|
||||
|
||||
run-task-run () {
|
||||
$PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py --remove_run_dir all
|
||||
}
|
||||
|
||||
run-modelsim () {
|
||||
$PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_modelsim.py "$@"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,148 +9,175 @@ PYTHON_EXEC=python3.8
|
|||
echo -e "Basic regression tests";
|
||||
|
||||
echo -e "Testing configuration chain of a K4N4 FPGA";
|
||||
run-task basic_tests/full_testbench/configuration_chain --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain_no_time_stamp --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain_config_enable_scff --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs
|
||||
run-task basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs
|
||||
run-task basic_tests/preconfig_testbench/configuration_chain_config_done_io --debug --show_thread_logs
|
||||
run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain $@
|
||||
run-task basic_tests/full_testbench/configuration_chain_no_time_stamp $@
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_reset $@
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_resetb $@
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_set $@
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_setb $@
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_set_reset $@
|
||||
run-task basic_tests/full_testbench/configuration_chain_config_enable_scff $@
|
||||
run-task basic_tests/full_testbench/multi_region_configuration_chain $@
|
||||
run-task basic_tests/full_testbench/fast_configuration_chain $@
|
||||
run-task basic_tests/full_testbench/fast_configuration_chain_use_set $@
|
||||
run-task basic_tests/full_testbench/smart_fast_configuration_chain $@
|
||||
run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain $@
|
||||
run-task basic_tests/preconfig_testbench/configuration_chain $@
|
||||
run-task basic_tests/preconfig_testbench/configuration_chain_config_done_io $@
|
||||
run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp $@
|
||||
|
||||
echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
|
||||
run-task basic_tests/full_testbench/configuration_frame --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/multi_region_configuration_frame --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_frame --debug --show_thread_logs
|
||||
run-task basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame $@
|
||||
run-task basic_tests/full_testbench/smart_fast_configuration_frame $@
|
||||
run-task basic_tests/full_testbench/fast_configuration_frame $@
|
||||
run-task basic_tests/full_testbench/fast_configuration_frame_use_set $@
|
||||
run-task basic_tests/full_testbench/configuration_frame_ccff $@
|
||||
run-task basic_tests/full_testbench/configuration_frame_scff $@
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_reset $@
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_resetb $@
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_set $@
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_setb $@
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_set_reset $@
|
||||
run-task basic_tests/full_testbench/multi_region_configuration_frame $@
|
||||
run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_frame $@
|
||||
run-task basic_tests/preconfig_testbench/configuration_frame $@
|
||||
|
||||
echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
|
||||
run-task basic_tests/full_testbench/memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/memory_bank $@
|
||||
run-task basic_tests/full_testbench/memory_bank_use_reset $@
|
||||
run-task basic_tests/full_testbench/memory_bank_use_resetb $@
|
||||
run-task basic_tests/full_testbench/memory_bank_use_set $@
|
||||
run-task basic_tests/full_testbench/memory_bank_use_setb $@
|
||||
run-task basic_tests/full_testbench/memory_bank_use_set_reset $@
|
||||
run-task basic_tests/full_testbench/multi_region_memory_bank $@
|
||||
run-task basic_tests/full_testbench/fast_memory_bank $@
|
||||
run-task basic_tests/full_testbench/fast_memory_bank_use_set $@
|
||||
run-task basic_tests/full_testbench/smart_fast_memory_bank $@
|
||||
run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank $@
|
||||
run-task basic_tests/preconfig_testbench/memory_bank $@
|
||||
|
||||
echo -e "Testing physical design friendly memory bank configuration protocol of a K4N4 FPGA";
|
||||
run-task basic_tests/full_testbench/ql_memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/ql_memory_bank_use_wlr --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/multi_region_ql_memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/ql_memory_bank_flatten --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/ql_memory_bank_shift_register --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/ql_memory_bank_shift_register_multi_chain --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/ql_memory_bank $@
|
||||
run-task basic_tests/full_testbench/ql_memory_bank_use_wlr $@
|
||||
run-task basic_tests/full_testbench/multi_region_ql_memory_bank $@
|
||||
run-task basic_tests/full_testbench/ql_memory_bank_flatten $@
|
||||
run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr $@
|
||||
run-task basic_tests/full_testbench/ql_memory_bank_shift_register $@
|
||||
run-task basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr $@
|
||||
run-task basic_tests/full_testbench/ql_memory_bank_shift_register_multi_chain $@
|
||||
|
||||
echo -e "Testing testbenches without self checking features";
|
||||
run-task basic_tests/full_testbench/full_testbench_without_self_checking --debug --show_thread_logs
|
||||
run-task basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/full_testbench_without_self_checking $@
|
||||
run-task basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking $@
|
||||
|
||||
echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
|
||||
run-task basic_tests/full_testbench/flatten_memory --debug --show_thread_logs
|
||||
run-task basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/flatten_memory $@
|
||||
run-task basic_tests/preconfig_testbench/flatten_memory $@
|
||||
|
||||
echo -e "Testing fixed device layout and routing channel width";
|
||||
run-task basic_tests/fixed_device_support --debug --show_thread_logs
|
||||
run-task basic_tests/fixed_device_support $@
|
||||
|
||||
echo -e "Testing fabric Verilog generation only";
|
||||
run-task basic_tests/generate_fabric --debug --show_thread_logs
|
||||
run-task basic_tests/generate_fabric $@
|
||||
|
||||
echo -e "Testing Verilog testbench generation only";
|
||||
run-task basic_tests/generate_testbench --debug --show_thread_logs
|
||||
run-task basic_tests/generate_testbench $@
|
||||
|
||||
echo -e "Testing separated Verilog fabric netlists and testbench locations";
|
||||
run-task basic_tests/custom_fabric_netlist_location --debug --show_thread_logs
|
||||
run-task basic_tests/custom_fabric_netlist_location $@
|
||||
|
||||
echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
|
||||
run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq --debug --show_thread_logs
|
||||
run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq $@
|
||||
# TODO: This feature is temporarily out of test due to the emergency in delivering netlists for multi-chain shift-register memory bank
|
||||
#run-task basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq --debug --show_thread_logs
|
||||
#run-task basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq $@
|
||||
|
||||
echo -e "Testing Secured FPGA fabrics";
|
||||
run-task basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/generate_random_key --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/generate_random_key_ql_memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/load_external_key --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/load_external_key_qlbank_fpga --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/load_external_key_qlbanksr_multi_chain_fpga --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/generate_vanilla_key $@
|
||||
run-task basic_tests/fabric_key/generate_multi_region_vanilla_key $@
|
||||
run-task basic_tests/fabric_key/generate_random_key $@
|
||||
run-task basic_tests/fabric_key/generate_random_key_ql_memory_bank $@
|
||||
run-task basic_tests/fabric_key/load_external_key $@
|
||||
run-task basic_tests/fabric_key/load_external_key_cc_fpga $@
|
||||
run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga $@
|
||||
run-task basic_tests/fabric_key/load_external_key_qlbank_fpga $@
|
||||
run-task basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga $@
|
||||
run-task basic_tests/fabric_key/load_external_key_qlbanksr_multi_chain_fpga $@
|
||||
# TODO: This feature is temporarily out of test due to the emergency in delivering netlists for multi-chain shift-register memory bank
|
||||
#run-task basic_tests/fabric_key/load_external_key_multi_region_qlbanksr_fpga --debug --show_thread_logs
|
||||
#run-task basic_tests/fabric_key/load_external_key_multi_region_qlbanksr_fpga $@
|
||||
|
||||
echo -e "Testing K4 series FPGA";
|
||||
echo -e "Testing K4N4 with facturable LUTs";
|
||||
run-task basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_frac_lut $@
|
||||
echo -e "Testing K4N4 with asynchronous reset";
|
||||
run-task basic_tests/k4_series/k4n4_fracff --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_fracff $@
|
||||
echo -e "Testing K4N4 with negative edge clocks";
|
||||
run-task basic_tests/k4_series/k4n4_fracff2edge --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_fracff2edge $@
|
||||
echo -e "Testing K4N4 with hard adders";
|
||||
run-task basic_tests/k4_series/k4n4_adder --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_adder $@
|
||||
echo -e "Testing K4N4 without local routing architecture";
|
||||
run-task basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_no_local_routing $@
|
||||
echo -e "Testing K4N4 with block RAM";
|
||||
run-task basic_tests/k4_series/k4n4_bram --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_bram $@
|
||||
echo -e "Testing K4N4 with LUTRAM";
|
||||
run-task basic_tests/k4_series/k4n4_lutram --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_lutram $@
|
||||
echo -e "Testing K4N4 with multiple lengths of routing segments";
|
||||
run-task basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_L124 $@
|
||||
echo -e "Testing K4N4 with 32-bit fracturable multiplier";
|
||||
run-task basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_frac_mult $@
|
||||
echo -e "Testing K4N5 with pattern based local routing";
|
||||
run-task basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n5_pattern_local_routing $@
|
||||
|
||||
echo -e "Testing different tile organizations";
|
||||
echo -e "Testing tiles with pins only on top and left sides";
|
||||
run-task basic_tests/tile_organization/top_left_custom_pins --debug --show_thread_logs
|
||||
run-task basic_tests/tile_organization/top_left_custom_pins $@
|
||||
echo -e "Testing tiles with pins only on top and right sides";
|
||||
run-task basic_tests/tile_organization/top_right_custom_pins --debug --show_thread_logs
|
||||
run-task basic_tests/tile_organization/top_right_custom_pins $@
|
||||
echo -e "Testing tiles with pins only on bottom and right sides";
|
||||
run-task basic_tests/tile_organization/bottom_right_custom_pins --debug --show_thread_logs
|
||||
run-task basic_tests/tile_organization/bottom_right_custom_pins $@
|
||||
echo -e "Testing tiles with I/O in center grid";
|
||||
run-task basic_tests/tile_organization/tileable_io --debug --show_thread_logs
|
||||
run-task basic_tests/tile_organization/tileable_io $@
|
||||
|
||||
echo -e "Testing global port definition from tiles";
|
||||
run-task basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs
|
||||
run-task basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs
|
||||
run-task basic_tests/global_tile_ports/global_tile_4clock --debug --show_thread_logs
|
||||
run-task basic_tests/global_tile_ports/global_tile_4clock_pin --debug --show_thread_logs
|
||||
run-task basic_tests/global_tile_ports/global_tile_clock $@
|
||||
run-task basic_tests/global_tile_ports/global_tile_reset $@
|
||||
run-task basic_tests/global_tile_ports/global_tile_4clock $@
|
||||
run-task basic_tests/global_tile_ports/global_tile_4clock_pin $@
|
||||
|
||||
echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific";
|
||||
run-task basic_tests/verific_test --debug --show_thread_logs
|
||||
run-task basic_tests/verific_test $@
|
||||
|
||||
echo -e "Testing explicit multi verilog files";
|
||||
run-task basic_tests/explicit_multi_verilog_files --debug --show_thread_logs
|
||||
run-task basic_tests/explicit_multi_verilog_files $@
|
||||
|
||||
echo -e "Test the remove of runtime directories"
|
||||
clear-task-run basic_tests/explicit_multi_verilog_files $@
|
||||
|
||||
echo -e "Testing write GSB to files";
|
||||
run-task basic_tests/write_gsb/write_gsb_to_xml $@
|
||||
run-task basic_tests/write_gsb/write_gsb_to_xml_compress_routing $@
|
||||
run-task basic_tests/write_gsb/write_unique_gsb_to_xml $@
|
||||
run-task basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing $@
|
||||
|
||||
echo -e "Testing bus group features";
|
||||
run-task basic_tests/bus_group/preconfig_testbench_explicit_mapping $@
|
||||
run-task basic_tests/bus_group/preconfig_testbench_implicit_mapping $@
|
||||
run-task basic_tests/bus_group/full_testbench_explicit_mapping $@
|
||||
run-task basic_tests/bus_group/full_testbench_implicit_mapping $@
|
||||
|
||||
echo -e "Testing fix pins features";
|
||||
run-task basic_tests/fix_pins $@
|
||||
|
||||
echo -e "Testing project templates";
|
||||
run-task template_tasks/vpr_blif_template $@
|
||||
run-task template_tasks/yosys_vpr_template $@
|
||||
run-task template_tasks/vtr_benchmarks_template $@
|
||||
|
||||
echo -e "Testing create tsk from template and run task"
|
||||
create-task _task_copy basic_tests/generate_fabric
|
||||
run-task _task_copy
|
||||
|
||||
echo -e "Testing output files without time stamp";
|
||||
run-task basic_tests/no_time_stamp --debug --show_thread_logs
|
||||
run-task basic_tests/no_time_stamp $@
|
||||
# Run git-diff to ensure no changes on the golden netlists
|
||||
git diff --name-status -- ':openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/**'
|
||||
if git diff --name-status --exit-code -- ':openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/**'; then
|
||||
|
|
@ -159,33 +186,8 @@ else
|
|||
echo -e "Detect changes in golden netlists"; exit 1;
|
||||
fi
|
||||
|
||||
echo -e "Test the remove of runtime directories"
|
||||
run-task basic_tests/explicit_multi_verilog_files --debug --show_thread_logs --remove_run_dir all
|
||||
|
||||
# Repgression test to test multi-user enviroment
|
||||
# Note: Keep this task as the last one!!!
|
||||
cp -r */*/basic_tests/full_testbench/configuration_chain /tmp/
|
||||
cd /tmp/ && run-task configuration_chain --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing write GSB to files";
|
||||
run-task basic_tests/write_gsb/write_gsb_to_xml --debug --show_thread_logs
|
||||
run-task basic_tests/write_gsb/write_gsb_to_xml_compress_routing --debug --show_thread_logs
|
||||
run-task basic_tests/write_gsb/write_unique_gsb_to_xml --debug --show_thread_logs
|
||||
run-task basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing bus group features";
|
||||
run-task basic_tests/bus_group/preconfig_testbench_explicit_mapping --debug --show_thread_logs
|
||||
run-task basic_tests/bus_group/preconfig_testbench_implicit_mapping --debug --show_thread_logs
|
||||
run-task basic_tests/bus_group/full_testbench_explicit_mapping --debug --show_thread_logs
|
||||
run-task basic_tests/bus_group/full_testbench_implicit_mapping --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing fix pins features";
|
||||
run-task basic_tests/fix_pins --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing project templates";
|
||||
run-task template_tasks/vpr_blif_template --debug --show_thread_logs
|
||||
run-task template_tasks/yosys_vpr_template --debug --show_thread_logs
|
||||
run-task template_tasks/vtr_benchmarks_template --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing create tsk from template and run task"
|
||||
create-task _task_copy basic_tests/generate_fabric
|
||||
run-task _task_copy
|
||||
cd /tmp/ && run-task configuration_chain $@
|
||||
cd -
|
||||
|
|
|
|||
|
|
@ -9,8 +9,9 @@ PYTHON_EXEC=python3.8
|
|||
echo -e "Basic regression tests for Yosys-only flow";
|
||||
|
||||
echo -e "Testing configuration chain of a K4N4 FPGA";
|
||||
run-task basic_tests/yosys_only --debug --show_thread_logs
|
||||
run-task basic_tests/yosys_only $@
|
||||
|
||||
# Repgression test to test multi-user enviroment
|
||||
cp -r */*/basic_tests/yosys_only /tmp/
|
||||
cd /tmp/ && run-task yosys_only --debug --show_thread_logs
|
||||
cd /tmp/ && run-task yosys_only $@
|
||||
cd -
|
||||
|
|
|
|||
|
|
@ -9,30 +9,30 @@ PYTHON_EXEC=python3.8
|
|||
echo -e "FPGA-Bitstream regression tests";
|
||||
|
||||
echo -e "Testing bitstream generation for an auto-sized device";
|
||||
run-task fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs
|
||||
run-task fpga_bitstream/generate_bitstream/device_auto $@
|
||||
|
||||
echo -e "Testing bitstream generation for an 48x48 FPGA device";
|
||||
run-task fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs
|
||||
run-task fpga_bitstream/generate_bitstream/device_48x48 $@
|
||||
|
||||
echo -e "Testing bitstream generation for an 96x96 FPGA device";
|
||||
run-task fpga_bitstream/generate_bitstream/device_96x96 --debug --show_thread_logs
|
||||
run-task fpga_bitstream/generate_bitstream/device_96x96 $@
|
||||
|
||||
echo -e "Testing loading architecture bitstream from an external file";
|
||||
run-task fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs
|
||||
run-task fpga_bitstream/load_external_architecture_bitstream $@
|
||||
|
||||
echo -e "Testing repacker capability in identifying wire LUTs";
|
||||
run-task fpga_bitstream/repack_wire_lut --debug --show_thread_logs
|
||||
run-task fpga_bitstream/repack_wire_lut $@
|
||||
|
||||
echo -e "Testing overloading default paths for programmable interconnect when generating bitstream";
|
||||
run-task fpga_bitstream/overload_mux_default_path --debug --show_thread_logs
|
||||
run-task fpga_bitstream/overload_mux_default_path $@
|
||||
|
||||
echo -e "Testing outputting I/O mapping result to file";
|
||||
run-task fpga_bitstream/write_io_mapping --debug --show_thread_logs
|
||||
run-task fpga_bitstream/write_io_mapping $@
|
||||
|
||||
echo -e "Testing report bitstream distribution to file";
|
||||
run-task fpga_bitstream/report_bitstream_distribution/default_depth --debug --show_thread_logs
|
||||
run-task fpga_bitstream/report_bitstream_distribution/custom_depth --debug --show_thread_logs
|
||||
run-task fpga_bitstream/report_bitstream_distribution/default_depth $@
|
||||
run-task fpga_bitstream/report_bitstream_distribution/custom_depth $@
|
||||
|
||||
echo -e "Testing bitstream file with don't care bits";
|
||||
run-task fpga_bitstream/dont_care_bits/ql_memory_bank_flatten --debug --show_thread_logs
|
||||
run-task fpga_bitstream/dont_care_bits/ql_memory_bank_shift_register --debug --show_thread_logs
|
||||
run-task fpga_bitstream/dont_care_bits/ql_memory_bank_flatten $@
|
||||
run-task fpga_bitstream/dont_care_bits/ql_memory_bank_shift_register $@
|
||||
|
|
|
|||
|
|
@ -9,12 +9,12 @@ PYTHON_EXEC=python3.8
|
|||
echo -e "FPGA-SDC regression tests";
|
||||
|
||||
echo -e "Testing SDC generation with time units";
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_as --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_fs --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ps --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ns --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_us --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ms --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_default --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ks --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_Ms --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_as $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_fs $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ps $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ns $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_us $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ms $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_default $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ks $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_Ms $@
|
||||
|
|
|
|||
|
|
@ -9,4 +9,4 @@ PYTHON_EXEC=python3.8
|
|||
echo -e "FPGA-SPICE regression tests";
|
||||
|
||||
echo -e "Testing FPGA-SPICE with netlist generation";
|
||||
run-task fpga_spice/generate_spice --debug --show_thread_logs
|
||||
run-task fpga_spice/generate_spice $@
|
||||
|
|
|
|||
|
|
@ -9,141 +9,141 @@ PYTHON_EXEC=python3.8
|
|||
echo -e "FPGA-Verilog Feature Tests";
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
|
||||
run-task fpga_verilog/lut_design/single_mode --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/single_mode $@
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 ";
|
||||
run-task fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_lut4 $@
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: fracturable LUT4 with embedded carry logic";
|
||||
run-task fpga_verilog/lut_design/frac_lut4_arith --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_lut4_arith $@
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: native fracturable LUT4 ";
|
||||
run-task fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_native_lut4 $@
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes";
|
||||
run-task fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_lut4_and_switch $@
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 ";
|
||||
run-task fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_lut6 $@
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers";
|
||||
run-task fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/intermediate_buffer $@
|
||||
|
||||
echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
|
||||
run-task fpga_verilog/untileable --debug --show_thread_logs
|
||||
run-task fpga_verilog/untileable $@
|
||||
|
||||
echo -e "Testing Verilog generation with hard adder chain in CLBs ";
|
||||
run-task fpga_verilog/adder/hard_adder --debug --show_thread_logs
|
||||
run-task fpga_verilog/adder/hard_adder $@
|
||||
|
||||
echo -e "Testing Verilog generation with soft adder chain in CLBs ";
|
||||
run-task fpga_verilog/adder/soft_adder --debug --show_thread_logs
|
||||
run-task fpga_verilog/adder/soft_adder $@
|
||||
|
||||
echo -e "Testing Verilog generation with 1k block RAMs ";
|
||||
run-task fpga_verilog/bram/dpram1k --debug --show_thread_logs
|
||||
run-task fpga_verilog/bram/dpram1k $@
|
||||
|
||||
echo -e "Testing Verilog generation with 1k block RAMs spanning two columns ";
|
||||
run-task fpga_verilog/bram/wide_dpram1k --debug --show_thread_logs
|
||||
run-task fpga_verilog/bram/wide_dpram1k $@
|
||||
|
||||
echo -e "Testing Verilog generation with heterogeneous fabric using 8-bit single-mode multipliers ";
|
||||
run-task fpga_verilog/dsp/single_mode_mult_8x8 --debug --show_thread_logs
|
||||
run-task fpga_verilog/dsp/single_mode_mult_8x8 $@
|
||||
|
||||
echo -e "Testing Verilog generation with heterogeneous fabric using 16-bit multi-mode multipliers ";
|
||||
run-task fpga_verilog/dsp/multi_mode_mult_16x16 --debug --show_thread_logs
|
||||
run-task fpga_verilog/dsp/multi_mode_mult_16x16 $@
|
||||
|
||||
echo -e "Testing Verilog generation with heterogeneous fabric using multi-width 16-bit multi-mode multipliers ";
|
||||
run-task fpga_verilog/dsp/wide_multi_mode_mult_16x16 --debug --show_thread_logs
|
||||
run-task fpga_verilog/dsp/wide_multi_mode_mult_16x16 $@
|
||||
|
||||
echo -e "Testing Verilog generation with heterogeneous fabric using 8-bit single-mode registerable multipliers ";
|
||||
run-task fpga_verilog/dsp/single_mode_mult_8x8_reg --debug --show_thread_logs
|
||||
run-task fpga_verilog/dsp/single_mode_mult_8x8_reg $@
|
||||
|
||||
echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
|
||||
run-task fpga_verilog/io/multi_io_capacity --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/multi_io_capacity $@
|
||||
|
||||
echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
|
||||
run-task fpga_verilog/io/reduced_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/reduced_io $@
|
||||
|
||||
echo -e "Testing Verilog generation with embedded I/Os for an FPGA ";
|
||||
run-task fpga_verilog/io/embedded_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/embedded_io $@
|
||||
|
||||
echo -e "Testing Verilog generation with SoC I/Os for an FPGA ";
|
||||
run-task fpga_verilog/io/soc_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/soc_io $@
|
||||
|
||||
echo -e "Testing Verilog generation with registerable I/Os for an FPGA ";
|
||||
run-task fpga_verilog/io/registerable_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/registerable_io $@
|
||||
|
||||
echo -e "Testing Verilog generation with adder chain across an FPGA";
|
||||
run-task fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs
|
||||
run-task fpga_verilog/fabric_chain/adder_chain $@
|
||||
|
||||
echo -e "Testing Verilog generation with shift register chain across an FPGA";
|
||||
run-task fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs
|
||||
run-task fpga_verilog/fabric_chain/register_chain $@
|
||||
|
||||
echo -e "Testing Verilog generation with scan chain across an FPGA";
|
||||
run-task fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs
|
||||
run-task fpga_verilog/fabric_chain/scan_chain $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure";
|
||||
run-task fpga_verilog/mux_design/tree_structure --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/tree_structure $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2";
|
||||
run-task fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/stdcell_mux2 $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
|
||||
run-task fpga_verilog/mux_design/local_encoder --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/local_encoder $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers without buffers";
|
||||
run-task fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/debuf_mux $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
|
||||
run-task fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/inbuf_only_mux $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers with output buffers only";
|
||||
run-task fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/outbuf_only_mux $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers with constant gnd input";
|
||||
run-task fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/const_input_gnd $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers without constant inputs";
|
||||
run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/no_const_input $@
|
||||
|
||||
echo -e "Testing Verilog generation with behavioral description";
|
||||
run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog_default_nettype_wire --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog $@
|
||||
run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog_default_nettype_wire $@
|
||||
|
||||
echo -e "Testing synthesizable Verilog generation with external standard cells";
|
||||
run-task fpga_verilog/verilog_netlist_formats/synthesizable_verilog --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/synthesizable_verilog $@
|
||||
|
||||
echo -e "Testing implicit Verilog generation";
|
||||
run-task fpga_verilog/verilog_netlist_formats/implicit_verilog --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/implicit_verilog $@
|
||||
run-task fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire $@
|
||||
|
||||
echo -e "Testing explicit Verilog generation";
|
||||
run-task fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire $@
|
||||
|
||||
echo -e "Testing Verilog generation with flatten routing modules";
|
||||
run-task fpga_verilog/flatten_routing --debug --show_thread_logs
|
||||
run-task fpga_verilog/flatten_routing $@
|
||||
|
||||
echo -e "Testing Verilog generation with duplicated grid output pins";
|
||||
run-task fpga_verilog/duplicated_grid_pin --debug --show_thread_logs
|
||||
run-task fpga_verilog/duplicated_grid_pin $@
|
||||
|
||||
echo -e "Testing Verilog generation with spy output pads";
|
||||
run-task fpga_verilog/spypad --debug --show_thread_logs
|
||||
run-task fpga_verilog/spypad $@
|
||||
|
||||
echo -e "Testing Power-gating designs";
|
||||
run-task fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug
|
||||
|
||||
echo -e "Testing Depopulated crossbar in local routing";
|
||||
run-task fpga_verilog/depopulate_crossbar --debug --show_thread_logs
|
||||
run-task fpga_verilog/depopulate_crossbar $@
|
||||
|
||||
echo -e "Testing Fully connected output crossbar in local routing";
|
||||
run-task fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
|
||||
run-task fpga_verilog/fully_connected_output_crossbar $@
|
||||
|
||||
echo -e "Testing through channels in tileable routing";
|
||||
run-task fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
|
||||
run-task fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
|
||||
run-task fpga_verilog/thru_channel/thru_narrow_tile $@
|
||||
run-task fpga_verilog/thru_channel/thru_wide_tile $@
|
||||
|
||||
echo -e "Testing the generation of preconfigured fabric wrapper for different HDL simulators";
|
||||
run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_none --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_none $@
|
||||
run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim $@
|
||||
|
||||
echo -e "Testing the netlist generation by forcing the use of relative paths";
|
||||
run-task fpga_verilog/verilog_netlist_formats/use_relative_path --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/preconfig_testbench_use_relative_path --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/use_relative_path $@
|
||||
run-task fpga_verilog/verilog_netlist_formats/preconfig_testbench_use_relative_path $@
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ PYTHON_EXEC=python3.8
|
|||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "IWLS'05 benchmark regression tests";
|
||||
run-task benchmark_sweep/iwls2005 --debug --show_thread_logs
|
||||
run-task benchmark_sweep/iwls2005 $@
|
||||
# Run a quick but relaxed QoR check for heterogeneous blocks
|
||||
#python3 openfpga_flow/scripts/check_qor.py --reference_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv --check_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/latest/task_result.csv --metric_checklist_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv --check_tolerance 0.2,100
|
||||
python3 openfpga_flow/scripts/check_qor.py --reference_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv --check_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/latest/task_result.csv --metric_checklist_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/config/metric_checklist.csv --check_tolerance 0.2,100
|
||||
|
|
|
|||
|
|
@ -7,15 +7,15 @@ PYTHON_EXEC=python3.8
|
|||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "Micro benchmark regression tests";
|
||||
run-task benchmark_sweep/counter8 --debug --show_thread_logs
|
||||
run-task benchmark_sweep/counter8_full_testbench --debug --show_thread_logs
|
||||
run-task benchmark_sweep/counter128 --debug --show_thread_logs
|
||||
run-task benchmark_sweep/mac_units --debug --show_thread_logs
|
||||
run-task benchmark_sweep/counter8 $@
|
||||
run-task benchmark_sweep/counter8_full_testbench $@
|
||||
run-task benchmark_sweep/counter128 $@
|
||||
run-task benchmark_sweep/mac_units $@
|
||||
|
||||
# Verify MCNC big20 benchmark suite with ModelSim
|
||||
# Please make sure you have ModelSim installed in the environment
|
||||
# Otherwise, it will fail
|
||||
run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
|
||||
run-task benchmark_sweep/mcnc_big20 $@
|
||||
#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
|
||||
|
||||
run-task benchmark_sweep/signal_gen --debug --show_thread_logs
|
||||
run-task benchmark_sweep/signal_gen $@
|
||||
|
|
|
|||
|
|
@ -9,11 +9,11 @@ PYTHON_EXEC=python3.8
|
|||
echo -e "QuickLogic regression tests";
|
||||
|
||||
echo -e "Testing yosys flow using custom ys script for running quicklogic device";
|
||||
run-task quicklogic_tests/flow_test --debug --show_thread_logs
|
||||
run-task quicklogic_tests/flow_test $@
|
||||
|
||||
echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device";
|
||||
run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs
|
||||
run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs
|
||||
run-task quicklogic_tests/counter_5clock_test $@
|
||||
run-task quicklogic_tests/sdc_controller_test $@
|
||||
|
||||
echo -e "Testing yosys flow using custom ys script for adders in quicklogic device";
|
||||
run-task quicklogic_tests/lut_adder_test --debug --show_thread_logs
|
||||
run-task quicklogic_tests/lut_adder_test $@
|
||||
|
|
|
|||
|
|
@ -7,6 +7,6 @@ PYTHON_EXEC=python3.8
|
|||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "VTR benchmark regression tests";
|
||||
run-task benchmark_sweep/vtr_benchmarks --debug --show_thread_logs
|
||||
run-task benchmark_sweep/vtr_benchmarks $@
|
||||
# Run a quick but relaxed QoR check for heterogeneous blocks
|
||||
python3 openfpga_flow/scripts/check_qor.py --reference_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv --check_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/latest/task_result.csv --metric_checklist_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv --check_tolerance 0.2,100
|
||||
|
|
|
|||
Loading…
Reference in New Issue