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Update frac_mem_32k.v

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Yunus Emre ERYILMAZ 2022-10-12 09:35:35 +03:00 committed by GitHub
parent d79ada8720
commit f62d435b1e
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1 changed files with 7 additions and 3 deletions
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openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v
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@ -161,13 +161,17 @@ module frac_mem_32k (
end else if (4'b0111 == mode) begin
if (we_a) begin
ram_a[addr_a[0:9]] <= data_a;
ram_b[addr_b[0:9]] <= data_b;
q_a <= data_a;
q_b <= data_b;
end else begin
q_a <= ram_a[addr_a[0:9]];
end
if (we_b) begin
ram_b[addr_b[0:9]] <= data_b;
q_b <= data_b;
end else begin
q_b <= ram_b[addr_b[0:9]];
end
end
// Operating mode: dual port RAM 2048 x 16
end else if (4'b1000 == mode) begin
if (we_a) begin