[Test] Add golden reference for files outputted without time stamp
This commit is contained in:
tangxifan
parent
2bee59c6ca
commit
6e778a74ee
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@ -32,5 +32,3 @@ bench_read_verilog_options_common = -nolatches
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bench0_top = and2
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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vpr_fpga_verilog_formal_verification_top_netlist=
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@ -0,0 +1,123 @@
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: FPGA Verilog Testbench for Formal Top-level netlist of Design: and2
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// Author: Xifan TANG
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// Organization: University of Utah
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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//----- Default net type -----
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`default_nettype none
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module and2_top_formal_verification_random_tb;
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// ----- Default clock port is added here since benchmark does not contain one -------
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reg [0:0] clk;
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// ----- Shared inputs -------
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reg [0:0] a;
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reg [0:0] b;
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// ----- FPGA fabric outputs -------
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wire [0:0] out_c_gfpga;
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// ----- Benchmark outputs -------
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wire [0:0] out_c_bench;
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// ----- Output vectors checking flags -------
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reg [0:0] out_c_flag;
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// ----- Error counter -------
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integer nb_error= 0;
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// ----- FPGA fabric instanciation -------
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and2_top_formal_verification FPGA_DUT(
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.a_fm(a),
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.b_fm(b),
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.out_c_fm(out_c_gfpga) );
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// ----- End FPGA Fabric Instanication -------
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// ----- Reference Benchmark Instanication -------
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and2 REF_DUT(
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.a(a),
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.b(b),
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.c(out_c_bench) );
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// ----- End reference Benchmark Instanication -------
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// ----- Clock 'clk' Initialization -------
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initial begin
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clk[0] <= 1'b0;
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while(1) begin
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#0.4537859857
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clk[0] <= !clk[0];
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end
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end
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// ----- Begin reset signal generation -----
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// ----- End reset signal generation -----
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// ----- Input Initialization -------
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initial begin
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a <= 1'b0;
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b <= 1'b0;
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out_c_flag[0] <= 1'b0;
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end
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// ----- Input Stimulus -------
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always@(negedge clk[0]) begin
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a <= $random;
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b <= $random;
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end
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// ----- Begin checking output vectors -------
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// ----- Skip the first falling edge of clock, it is for initialization -------
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reg [0:0] sim_start;
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always@(negedge clk[0]) begin
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if (1'b1 == sim_start[0]) begin
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sim_start[0] <= ~sim_start[0];
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end else begin
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if(!(out_c_gfpga === out_c_bench) && !(out_c_bench === 1'bx)) begin
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out_c_flag <= 1'b1;
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end else begin
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out_c_flag<= 1'b0;
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end
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end
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end
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always@(posedge out_c_flag) begin
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if(out_c_flag) begin
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nb_error = nb_error + 1;
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$display("Mismatch on out_c_gfpga at time = %t", $realtime);
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end
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end
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// ----- Begin output waveform to VCD file-------
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initial begin
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$dumpfile("and2_formal.vcd");
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$dumpvars(1, and2_top_formal_verification_random_tb);
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end
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// ----- END output waveform to VCD file -------
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initial begin
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sim_start[0] <= 1'b1;
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$timeformat(-9, 2, "ns", 20);
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$display("Simulation start");
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// ----- Can be changed by the user for his/her need -------
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#6.353003979
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if(nb_error == 0) begin
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$display("Simulation Succeed");
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end else begin
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$display("Simulation Failed with %d error(s)", nb_error);
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end
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$finish;
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end
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endmodule
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// ----- END Verilog module for and2_top_formal_verification_random_tb -----
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//----- Default net type -----
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`default_nettype none
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,16 @@
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Netlist Summary
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// Author: Xifan TANG
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// Organization: University of Utah
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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// ------ Include fabric top-level netlists -----
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`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fabric_netlists.v"
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`include "and2_output_verilog.v"
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`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_top_formal_verification.v"
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`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v"
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@ -0,0 +1,502 @@
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Verilog netlist for pre-configured FPGA fabric by design: and2
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// Author: Xifan TANG
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// Organization: University of Utah
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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//----- Default net type -----
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`default_nettype none
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module and2_top_formal_verification (
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input [0:0] a_fm,
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input [0:0] b_fm,
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output [0:0] out_c_fm);
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// ----- Local wires for FPGA fabric -----
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wire [0:31] gfpga_pad_GPIO_PAD;
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wire [0:0] ccff_head;
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wire [0:0] ccff_tail;
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wire [0:0] prog_clk;
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wire [0:0] set;
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wire [0:0] reset;
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wire [0:0] clk;
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// ----- FPGA top-level module to be capsulated -----
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fpga_top U0_formal_verification (
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.prog_clk(prog_clk[0]),
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.set(set[0]),
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.reset(reset[0]),
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.clk(clk[0]),
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.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0:31]),
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.ccff_head(ccff_head[0]),
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.ccff_tail(ccff_tail[0]));
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// ----- Begin Connect Global ports of FPGA top module -----
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assign set[0] = 1'b0;
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assign reset[0] = 1'b0;
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assign clk[0] = 1'b0;
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assign prog_clk[0] = 1'b0;
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// ----- End Connect Global ports of FPGA top module -----
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// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
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// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[6] -----
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assign gfpga_pad_GPIO_PAD[6] = a_fm[0];
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// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[1] -----
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assign gfpga_pad_GPIO_PAD[1] = b_fm[0];
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// ----- Blif Benchmark output out_c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[9] -----
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assign out_c_fm[0] = gfpga_pad_GPIO_PAD[9];
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// ----- Wire unused FPGA I/Os to constants -----
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assign gfpga_pad_GPIO_PAD[0] = 1'b0;
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assign gfpga_pad_GPIO_PAD[2] = 1'b0;
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assign gfpga_pad_GPIO_PAD[3] = 1'b0;
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assign gfpga_pad_GPIO_PAD[4] = 1'b0;
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assign gfpga_pad_GPIO_PAD[5] = 1'b0;
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assign gfpga_pad_GPIO_PAD[7] = 1'b0;
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assign gfpga_pad_GPIO_PAD[8] = 1'b0;
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assign gfpga_pad_GPIO_PAD[10] = 1'b0;
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assign gfpga_pad_GPIO_PAD[11] = 1'b0;
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assign gfpga_pad_GPIO_PAD[12] = 1'b0;
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assign gfpga_pad_GPIO_PAD[13] = 1'b0;
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assign gfpga_pad_GPIO_PAD[14] = 1'b0;
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assign gfpga_pad_GPIO_PAD[15] = 1'b0;
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assign gfpga_pad_GPIO_PAD[16] = 1'b0;
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assign gfpga_pad_GPIO_PAD[17] = 1'b0;
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assign gfpga_pad_GPIO_PAD[18] = 1'b0;
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assign gfpga_pad_GPIO_PAD[19] = 1'b0;
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assign gfpga_pad_GPIO_PAD[20] = 1'b0;
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assign gfpga_pad_GPIO_PAD[21] = 1'b0;
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assign gfpga_pad_GPIO_PAD[22] = 1'b0;
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assign gfpga_pad_GPIO_PAD[23] = 1'b0;
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assign gfpga_pad_GPIO_PAD[24] = 1'b0;
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assign gfpga_pad_GPIO_PAD[25] = 1'b0;
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assign gfpga_pad_GPIO_PAD[26] = 1'b0;
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assign gfpga_pad_GPIO_PAD[27] = 1'b0;
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assign gfpga_pad_GPIO_PAD[28] = 1'b0;
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assign gfpga_pad_GPIO_PAD[29] = 1'b0;
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assign gfpga_pad_GPIO_PAD[30] = 1'b0;
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assign gfpga_pad_GPIO_PAD[31] = 1'b0;
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// ----- Begin load bitstream to configuration memories -----
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// ----- Begin assign bitstream to configuration memories -----
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initial begin
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000;
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111;
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01;
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10;
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_2.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_2.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_3.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_3.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_0.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_0.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_1.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_1.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_2.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_2.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_3.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_3.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_0.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_0.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_1.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_1.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
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force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b0011;
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b1100;
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_12.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_12.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_14.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_20.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_8.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_22.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_24.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_13.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_13.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_15.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_15.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_19.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_21.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_23.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_25.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_13.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_13.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_15.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_13.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_13.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_15.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_15.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_19.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_21.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_23.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_outb[0:1] = 2'b01;
|
||||
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_6.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_6.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:2] = 3'b010;
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:2] = 3'b101;
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_3.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_3.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_4.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_4.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_5.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_5.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_6.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_6.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_7.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_7.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
end
|
||||
// ----- End assign bitstream to configuration memories -----
|
||||
// ----- End load bitstream to configuration memories -----
|
||||
endmodule
|
||||
// ----- END Verilog module for and2_top_formal_verification -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
<!--
|
||||
- Report Architecture Bitstream Distribution
|
||||
- Version: 1.0.3764-dev+dd400579-dirty
|
||||
-->
|
||||
|
||||
<block name="fpga_top" number_of_bits="527">
|
||||
<block name="grid_clb_1__1_" number_of_bits="136">
|
||||
</block>
|
||||
<block name="grid_io_top_1__2_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_right_2__1_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_bottom_1__0_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_left_0__1_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="sb_0__0_" number_of_bits="58">
|
||||
</block>
|
||||
<block name="sb_0__1_" number_of_bits="57">
|
||||
</block>
|
||||
<block name="sb_1__0_" number_of_bits="59">
|
||||
</block>
|
||||
<block name="sb_1__1_" number_of_bits="56">
|
||||
</block>
|
||||
<block name="cbx_1__0_" number_of_bits="33">
|
||||
</block>
|
||||
<block name="cbx_1__1_" number_of_bits="33">
|
||||
</block>
|
||||
<block name="cby_0__1_" number_of_bits="30">
|
||||
</block>
|
||||
<block name="cby_1__1_" number_of_bits="33">
|
||||
</block>
|
||||
</block>
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,86 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable configurable memory outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
|
||||
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
|
||||
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
|
||||
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
|
||||
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
|
||||
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_DFF_mem/DFF_*_/Q
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_DFF_mem/DFF_*_/QN
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mem_ble*_out_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mem_ble*_out_*/DFF_*_/QN
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/Q
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable configuration outputs of all the programmable cells for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_*_/sram
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_*_/sram_inv
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mux_ble*_out_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mux_ble*_out_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/sram
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/sram_inv
|
||||
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR
|
||||
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR
|
||||
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR
|
||||
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable routing multiplexer outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/out
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/out
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/out
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/out
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mux_ble*_out_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/out
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable Switch Block outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/ccff_tail
|
||||
|
||||
|
|
@ -0,0 +1,531 @@
|
|||
// Fabric bitstream
|
||||
// Version: 1.0.3764-dev+dd400579-dirty
|
||||
// Bitstream length: 527
|
||||
// Bitstream width (LSB -> MSB): 1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,53 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Fabric Netlist Summary
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ------ Include defines: preproc flags -----
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fpga_defines.v"
|
||||
|
||||
// ------ Include user-defined netlists -----
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/dff.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/gpio.v"
|
||||
// ------ Include primitive module netlists -----
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/arch_encoder.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/local_encoder.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/mux_primitives.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/muxes.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/luts.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/wires.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/memories.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v"
|
||||
|
||||
// ------ Include logic block netlists -----
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_top.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_right.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_bottom.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_left.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_clb.v"
|
||||
|
||||
// ------ Include routing module netlists -----
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_0__0_.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_0__1_.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_1__0_.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_1__1_.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cbx_1__0_.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cbx_1__1_.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cby_0__1_.v"
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cby_1__1_.v"
|
||||
|
||||
// ------ Include fabric top-level netlists -----
|
||||
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fpga_top.v"
|
||||
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Preprocessing flags to enable/disable features in FPGA Verilog modules
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
`define ENABLE_TIMING 1
|
||||
|
||||
|
|
@ -0,0 +1,463 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Top-level Verilog module for FPGA
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for fpga_top -----
|
||||
module fpga_top(prog_clk,
|
||||
set,
|
||||
reset,
|
||||
clk,
|
||||
gfpga_pad_GPIO_PAD,
|
||||
ccff_head,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] set;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] reset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] clk;
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:31] gfpga_pad_GPIO_PAD;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__0__0_ccff_tail;
|
||||
wire [0:12] cbx_1__0__0_chanx_left_out;
|
||||
wire [0:12] cbx_1__0__0_chanx_right_out;
|
||||
wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_;
|
||||
wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_;
|
||||
wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_;
|
||||
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_;
|
||||
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_;
|
||||
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_;
|
||||
wire [0:0] cbx_1__1__0_ccff_tail;
|
||||
wire [0:12] cbx_1__1__0_chanx_left_out;
|
||||
wire [0:12] cbx_1__1__0_chanx_right_out;
|
||||
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
wire [0:0] cby_0__1__0_ccff_tail;
|
||||
wire [0:12] cby_0__1__0_chany_bottom_out;
|
||||
wire [0:12] cby_0__1__0_chany_top_out;
|
||||
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
wire [0:0] cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_;
|
||||
wire [0:0] cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_;
|
||||
wire [0:0] cby_1__1__0_ccff_tail;
|
||||
wire [0:12] cby_1__1__0_chany_bottom_out;
|
||||
wire [0:12] cby_1__1__0_chany_top_out;
|
||||
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_;
|
||||
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_;
|
||||
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_;
|
||||
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
wire [0:0] grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_;
|
||||
wire [0:0] grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_;
|
||||
wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_;
|
||||
wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_;
|
||||
wire [0:0] grid_io_bottom_0_ccff_tail;
|
||||
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
wire [0:0] grid_io_left_0_ccff_tail;
|
||||
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
wire [0:0] grid_io_right_0_ccff_tail;
|
||||
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
wire [0:0] grid_io_top_0_ccff_tail;
|
||||
wire [0:0] sb_0__0__0_ccff_tail;
|
||||
wire [0:12] sb_0__0__0_chanx_right_out;
|
||||
wire [0:12] sb_0__0__0_chany_top_out;
|
||||
wire [0:0] sb_0__1__0_ccff_tail;
|
||||
wire [0:12] sb_0__1__0_chanx_right_out;
|
||||
wire [0:12] sb_0__1__0_chany_bottom_out;
|
||||
wire [0:0] sb_1__0__0_ccff_tail;
|
||||
wire [0:12] sb_1__0__0_chanx_left_out;
|
||||
wire [0:12] sb_1__0__0_chany_top_out;
|
||||
wire [0:0] sb_1__1__0_ccff_tail;
|
||||
wire [0:12] sb_1__1__0_chanx_left_out;
|
||||
wire [0:12] sb_1__1__0_chany_bottom_out;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
grid_clb grid_clb_1__1_ (
|
||||
.prog_clk(prog_clk),
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.top_width_0_height_0_subtile_0__pin_I_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_I_4_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_),
|
||||
.top_width_0_height_0_subtile_0__pin_I_8_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_),
|
||||
.right_width_0_height_0_subtile_0__pin_I_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_),
|
||||
.right_width_0_height_0_subtile_0__pin_I_5_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_),
|
||||
.right_width_0_height_0_subtile_0__pin_I_9_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_I_2_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_I_6_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_clk_0_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_),
|
||||
.left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
|
||||
.left_width_0_height_0_subtile_0__pin_I_7_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_),
|
||||
.ccff_head(cby_1__1__0_ccff_tail),
|
||||
.top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
|
||||
.right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_),
|
||||
.left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
grid_io_top grid_io_top_1__2_ (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0:7]),
|
||||
.bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.ccff_head(cbx_1__1__0_ccff_tail),
|
||||
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_tail(grid_io_top_0_ccff_tail));
|
||||
|
||||
grid_io_right grid_io_right_2__1_ (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[8:15]),
|
||||
.left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.ccff_head(grid_io_bottom_0_ccff_tail),
|
||||
.left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_tail(grid_io_right_0_ccff_tail));
|
||||
|
||||
grid_io_bottom grid_io_bottom_1__0_ (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[16:23]),
|
||||
.top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.ccff_head(ccff_head),
|
||||
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_tail(grid_io_bottom_0_ccff_tail));
|
||||
|
||||
grid_io_left grid_io_left_0__1_ (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[24:31]),
|
||||
.right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.right_width_0_height_0_subtile_4__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.right_width_0_height_0_subtile_5__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.right_width_0_height_0_subtile_6__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.right_width_0_height_0_subtile_7__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.ccff_head(cby_0__1__0_ccff_tail),
|
||||
.right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_tail(grid_io_left_0_ccff_tail));
|
||||
|
||||
sb_0__0_ sb_0__0_ (
|
||||
.prog_clk(prog_clk),
|
||||
.chany_top_in(cby_0__1__0_chany_bottom_out[0:12]),
|
||||
.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_),
|
||||
.chanx_right_in(cbx_1__0__0_chanx_left_out[0:12]),
|
||||
.right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_),
|
||||
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_head(sb_0__1__0_ccff_tail),
|
||||
.chany_top_out(sb_0__0__0_chany_top_out[0:12]),
|
||||
.chanx_right_out(sb_0__0__0_chanx_right_out[0:12]),
|
||||
.ccff_tail(sb_0__0__0_ccff_tail));
|
||||
|
||||
sb_0__1_ sb_0__1_ (
|
||||
.prog_clk(prog_clk),
|
||||
.chanx_right_in(cbx_1__1__0_chanx_left_out[0:12]),
|
||||
.right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
|
||||
.chany_bottom_in(cby_0__1__0_chany_top_out[0:12]),
|
||||
.bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_),
|
||||
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_head(grid_io_top_0_ccff_tail),
|
||||
.chanx_right_out(sb_0__1__0_chanx_right_out[0:12]),
|
||||
.chany_bottom_out(sb_0__1__0_chany_bottom_out[0:12]),
|
||||
.ccff_tail(sb_0__1__0_ccff_tail));
|
||||
|
||||
sb_1__0_ sb_1__0_ (
|
||||
.prog_clk(prog_clk),
|
||||
.chany_top_in(cby_1__1__0_chany_bottom_out[0:12]),
|
||||
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_),
|
||||
.top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.chanx_left_in(cbx_1__0__0_chanx_right_out[0:12]),
|
||||
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_),
|
||||
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_head(grid_io_left_0_ccff_tail),
|
||||
.chany_top_out(sb_1__0__0_chany_top_out[0:12]),
|
||||
.chanx_left_out(sb_1__0__0_chanx_left_out[0:12]),
|
||||
.ccff_tail(sb_1__0__0_ccff_tail));
|
||||
|
||||
sb_1__1_ sb_1__1_ (
|
||||
.prog_clk(prog_clk),
|
||||
.chany_bottom_in(cby_1__1__0_chany_top_out[0:12]),
|
||||
.bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_),
|
||||
.chanx_left_in(cbx_1__1__0_chanx_right_out[0:12]),
|
||||
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
|
||||
.ccff_head(grid_io_right_0_ccff_tail),
|
||||
.chany_bottom_out(sb_1__1__0_chany_bottom_out[0:12]),
|
||||
.chanx_left_out(sb_1__1__0_chanx_left_out[0:12]),
|
||||
.ccff_tail(sb_1__1__0_ccff_tail));
|
||||
|
||||
cbx_1__0_ cbx_1__0_ (
|
||||
.prog_clk(prog_clk),
|
||||
.chanx_left_in(sb_0__0__0_chanx_right_out[0:12]),
|
||||
.chanx_right_in(sb_1__0__0_chanx_left_out[0:12]),
|
||||
.ccff_head(sb_1__0__0_ccff_tail),
|
||||
.chanx_left_out(cbx_1__0__0_chanx_left_out[0:12]),
|
||||
.chanx_right_out(cbx_1__0__0_chanx_right_out[0:12]),
|
||||
.top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_),
|
||||
.top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_),
|
||||
.top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_),
|
||||
.bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.ccff_tail(cbx_1__0__0_ccff_tail));
|
||||
|
||||
cbx_1__1_ cbx_1__1_ (
|
||||
.prog_clk(prog_clk),
|
||||
.chanx_left_in(sb_0__1__0_chanx_right_out[0:12]),
|
||||
.chanx_right_in(sb_1__1__0_chanx_left_out[0:12]),
|
||||
.ccff_head(sb_1__1__0_ccff_tail),
|
||||
.chanx_left_out(cbx_1__1__0_chanx_left_out[0:12]),
|
||||
.chanx_right_out(cbx_1__1__0_chanx_right_out[0:12]),
|
||||
.top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_),
|
||||
.bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_),
|
||||
.bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_),
|
||||
.ccff_tail(cbx_1__1__0_ccff_tail));
|
||||
|
||||
cby_0__1_ cby_0__1_ (
|
||||
.prog_clk(prog_clk),
|
||||
.chany_bottom_in(sb_0__0__0_chany_top_out[0:12]),
|
||||
.chany_top_in(sb_0__1__0_chany_bottom_out[0:12]),
|
||||
.ccff_head(sb_0__0__0_ccff_tail),
|
||||
.chany_bottom_out(cby_0__1__0_chany_bottom_out[0:12]),
|
||||
.chany_top_out(cby_0__1__0_chany_top_out[0:12]),
|
||||
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
|
||||
.right_grid_left_width_0_height_0_subtile_0__pin_I_7_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_),
|
||||
.left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.ccff_tail(cby_0__1__0_ccff_tail));
|
||||
|
||||
cby_1__1_ cby_1__1_ (
|
||||
.prog_clk(prog_clk),
|
||||
.chany_bottom_in(sb_1__0__0_chany_top_out[0:12]),
|
||||
.chany_top_in(sb_1__1__0_chany_bottom_out[0:12]),
|
||||
.ccff_head(cbx_1__0__0_ccff_tail),
|
||||
.chany_bottom_out(cby_1__1__0_chany_bottom_out[0:12]),
|
||||
.chany_top_out(cby_1__1__0_chany_top_out[0:12]),
|
||||
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.left_grid_right_width_0_height_0_subtile_0__pin_I_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_),
|
||||
.left_grid_right_width_0_height_0_subtile_0__pin_I_5_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_),
|
||||
.left_grid_right_width_0_height_0_subtile_0__pin_I_9_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_),
|
||||
.ccff_tail(cby_1__1__0_ccff_tail));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for fpga_top -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Clock contraints for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 9.07571962e-10 -waveform {0 4.53785981e-10} [get_ports {clk[0]}]
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}]
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for physical tile: clb]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Grid Verilog module: grid_clb -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for grid_clb -----
|
||||
module grid_clb(prog_clk,
|
||||
set,
|
||||
reset,
|
||||
clk,
|
||||
top_width_0_height_0_subtile_0__pin_I_0_,
|
||||
top_width_0_height_0_subtile_0__pin_I_4_,
|
||||
top_width_0_height_0_subtile_0__pin_I_8_,
|
||||
right_width_0_height_0_subtile_0__pin_I_1_,
|
||||
right_width_0_height_0_subtile_0__pin_I_5_,
|
||||
right_width_0_height_0_subtile_0__pin_I_9_,
|
||||
bottom_width_0_height_0_subtile_0__pin_I_2_,
|
||||
bottom_width_0_height_0_subtile_0__pin_I_6_,
|
||||
bottom_width_0_height_0_subtile_0__pin_clk_0_,
|
||||
left_width_0_height_0_subtile_0__pin_I_3_,
|
||||
left_width_0_height_0_subtile_0__pin_I_7_,
|
||||
ccff_head,
|
||||
top_width_0_height_0_subtile_0__pin_O_2_,
|
||||
right_width_0_height_0_subtile_0__pin_O_3_,
|
||||
bottom_width_0_height_0_subtile_0__pin_O_0_,
|
||||
left_width_0_height_0_subtile_0__pin_O_1_,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] set;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] reset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_0__pin_I_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_0__pin_I_4_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_0__pin_I_8_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_0__pin_I_1_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_0__pin_I_5_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_0__pin_I_9_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_2_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_6_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_0__pin_clk_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_0__pin_I_3_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_0__pin_I_7_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_0__pin_O_2_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_0__pin_O_3_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_0__pin_O_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_0__pin_O_1_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
|
||||
.prog_clk(prog_clk),
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.clb_I({top_width_0_height_0_subtile_0__pin_I_0_, right_width_0_height_0_subtile_0__pin_I_1_, bottom_width_0_height_0_subtile_0__pin_I_2_, left_width_0_height_0_subtile_0__pin_I_3_, top_width_0_height_0_subtile_0__pin_I_4_, right_width_0_height_0_subtile_0__pin_I_5_, bottom_width_0_height_0_subtile_0__pin_I_6_, left_width_0_height_0_subtile_0__pin_I_7_, top_width_0_height_0_subtile_0__pin_I_8_, right_width_0_height_0_subtile_0__pin_I_9_}),
|
||||
.clb_clk(bottom_width_0_height_0_subtile_0__pin_clk_0_),
|
||||
.ccff_head(ccff_head),
|
||||
.clb_O({bottom_width_0_height_0_subtile_0__pin_O_0_, left_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, right_width_0_height_0_subtile_0__pin_O_3_}),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for grid_clb -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Grid Verilog module: grid_clb -----
|
||||
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for physical tile: io]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Grid Verilog module: grid_io_bottom -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for grid_io_bottom -----
|
||||
module grid_io_bottom(prog_clk,
|
||||
gfpga_pad_GPIO_PAD,
|
||||
top_width_0_height_0_subtile_0__pin_outpad_0_,
|
||||
top_width_0_height_0_subtile_1__pin_outpad_0_,
|
||||
top_width_0_height_0_subtile_2__pin_outpad_0_,
|
||||
top_width_0_height_0_subtile_3__pin_outpad_0_,
|
||||
top_width_0_height_0_subtile_4__pin_outpad_0_,
|
||||
top_width_0_height_0_subtile_5__pin_outpad_0_,
|
||||
top_width_0_height_0_subtile_6__pin_outpad_0_,
|
||||
top_width_0_height_0_subtile_7__pin_outpad_0_,
|
||||
ccff_head,
|
||||
top_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:7] gfpga_pad_GPIO_PAD;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
|
||||
.io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.ccff_head(ccff_head),
|
||||
.io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
|
||||
.io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
|
||||
.io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
|
||||
.io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
|
||||
.io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
|
||||
.io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
|
||||
.io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
|
||||
.io_outpad(top_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
|
||||
.io_inpad(top_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
|
||||
.io_outpad(top_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
|
||||
.io_inpad(top_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
|
||||
.io_outpad(top_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
|
||||
.io_inpad(top_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
|
||||
.io_outpad(top_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
|
||||
.io_inpad(top_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for grid_io_bottom -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Grid Verilog module: grid_io_bottom -----
|
||||
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for physical tile: io]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Grid Verilog module: grid_io_left -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for grid_io_left -----
|
||||
module grid_io_left(prog_clk,
|
||||
gfpga_pad_GPIO_PAD,
|
||||
right_width_0_height_0_subtile_0__pin_outpad_0_,
|
||||
right_width_0_height_0_subtile_1__pin_outpad_0_,
|
||||
right_width_0_height_0_subtile_2__pin_outpad_0_,
|
||||
right_width_0_height_0_subtile_3__pin_outpad_0_,
|
||||
right_width_0_height_0_subtile_4__pin_outpad_0_,
|
||||
right_width_0_height_0_subtile_5__pin_outpad_0_,
|
||||
right_width_0_height_0_subtile_6__pin_outpad_0_,
|
||||
right_width_0_height_0_subtile_7__pin_outpad_0_,
|
||||
ccff_head,
|
||||
right_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
right_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
right_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
right_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
right_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
right_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
right_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
right_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:7] gfpga_pad_GPIO_PAD;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
|
||||
.io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.ccff_head(ccff_head),
|
||||
.io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
|
||||
.io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
|
||||
.io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
|
||||
.io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
|
||||
.io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
|
||||
.io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
|
||||
.io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
|
||||
.io_outpad(right_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
|
||||
.io_inpad(right_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
|
||||
.io_outpad(right_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
|
||||
.io_inpad(right_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
|
||||
.io_outpad(right_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
|
||||
.io_inpad(right_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
|
||||
.io_outpad(right_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
|
||||
.io_inpad(right_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for grid_io_left -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Grid Verilog module: grid_io_left -----
|
||||
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for physical tile: io]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Grid Verilog module: grid_io_right -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for grid_io_right -----
|
||||
module grid_io_right(prog_clk,
|
||||
gfpga_pad_GPIO_PAD,
|
||||
left_width_0_height_0_subtile_0__pin_outpad_0_,
|
||||
left_width_0_height_0_subtile_1__pin_outpad_0_,
|
||||
left_width_0_height_0_subtile_2__pin_outpad_0_,
|
||||
left_width_0_height_0_subtile_3__pin_outpad_0_,
|
||||
left_width_0_height_0_subtile_4__pin_outpad_0_,
|
||||
left_width_0_height_0_subtile_5__pin_outpad_0_,
|
||||
left_width_0_height_0_subtile_6__pin_outpad_0_,
|
||||
left_width_0_height_0_subtile_7__pin_outpad_0_,
|
||||
ccff_head,
|
||||
left_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
left_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
left_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
left_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
left_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
left_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
left_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
left_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:7] gfpga_pad_GPIO_PAD;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
|
||||
.io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.ccff_head(ccff_head),
|
||||
.io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
|
||||
.io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
|
||||
.io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
|
||||
.io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
|
||||
.io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
|
||||
.io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
|
||||
.io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
|
||||
.io_outpad(left_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
|
||||
.io_inpad(left_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
|
||||
.io_outpad(left_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
|
||||
.io_inpad(left_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
|
||||
.io_outpad(left_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
|
||||
.io_inpad(left_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
|
||||
.io_outpad(left_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
|
||||
.io_inpad(left_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for grid_io_right -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Grid Verilog module: grid_io_right -----
|
||||
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for physical tile: io]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Grid Verilog module: grid_io_top -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for grid_io_top -----
|
||||
module grid_io_top(prog_clk,
|
||||
gfpga_pad_GPIO_PAD,
|
||||
bottom_width_0_height_0_subtile_0__pin_outpad_0_,
|
||||
bottom_width_0_height_0_subtile_1__pin_outpad_0_,
|
||||
bottom_width_0_height_0_subtile_2__pin_outpad_0_,
|
||||
bottom_width_0_height_0_subtile_3__pin_outpad_0_,
|
||||
bottom_width_0_height_0_subtile_4__pin_outpad_0_,
|
||||
bottom_width_0_height_0_subtile_5__pin_outpad_0_,
|
||||
bottom_width_0_height_0_subtile_6__pin_outpad_0_,
|
||||
bottom_width_0_height_0_subtile_7__pin_outpad_0_,
|
||||
ccff_head,
|
||||
bottom_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:7] gfpga_pad_GPIO_PAD;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.ccff_head(ccff_head),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for grid_io_top -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Grid Verilog module: grid_io_top -----
|
||||
|
||||
|
|
@ -0,0 +1,427 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for pb_type: clb
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Physical programmable logic block Verilog module: clb -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_clb_mode_clb_ -----
|
||||
module logical_tile_clb_mode_clb_(prog_clk,
|
||||
set,
|
||||
reset,
|
||||
clk,
|
||||
clb_I,
|
||||
clb_clk,
|
||||
ccff_head,
|
||||
clb_O,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] set;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] reset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:9] clb_I;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] clb_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:3] clb_O;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:9] clb_I;
|
||||
wire [0:0] clb_clk;
|
||||
wire [0:3] clb_O;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] direct_interc_4_out;
|
||||
wire [0:0] direct_interc_5_out;
|
||||
wire [0:0] direct_interc_6_out;
|
||||
wire [0:0] direct_interc_7_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_out;
|
||||
wire [0:0] mux_tree_size14_0_out;
|
||||
wire [0:3] mux_tree_size14_0_sram;
|
||||
wire [0:3] mux_tree_size14_0_sram_inv;
|
||||
wire [0:0] mux_tree_size14_10_out;
|
||||
wire [0:3] mux_tree_size14_10_sram;
|
||||
wire [0:3] mux_tree_size14_10_sram_inv;
|
||||
wire [0:0] mux_tree_size14_11_out;
|
||||
wire [0:3] mux_tree_size14_11_sram;
|
||||
wire [0:3] mux_tree_size14_11_sram_inv;
|
||||
wire [0:0] mux_tree_size14_12_out;
|
||||
wire [0:3] mux_tree_size14_12_sram;
|
||||
wire [0:3] mux_tree_size14_12_sram_inv;
|
||||
wire [0:0] mux_tree_size14_13_out;
|
||||
wire [0:3] mux_tree_size14_13_sram;
|
||||
wire [0:3] mux_tree_size14_13_sram_inv;
|
||||
wire [0:0] mux_tree_size14_14_out;
|
||||
wire [0:3] mux_tree_size14_14_sram;
|
||||
wire [0:3] mux_tree_size14_14_sram_inv;
|
||||
wire [0:0] mux_tree_size14_15_out;
|
||||
wire [0:3] mux_tree_size14_15_sram;
|
||||
wire [0:3] mux_tree_size14_15_sram_inv;
|
||||
wire [0:0] mux_tree_size14_1_out;
|
||||
wire [0:3] mux_tree_size14_1_sram;
|
||||
wire [0:3] mux_tree_size14_1_sram_inv;
|
||||
wire [0:0] mux_tree_size14_2_out;
|
||||
wire [0:3] mux_tree_size14_2_sram;
|
||||
wire [0:3] mux_tree_size14_2_sram_inv;
|
||||
wire [0:0] mux_tree_size14_3_out;
|
||||
wire [0:3] mux_tree_size14_3_sram;
|
||||
wire [0:3] mux_tree_size14_3_sram_inv;
|
||||
wire [0:0] mux_tree_size14_4_out;
|
||||
wire [0:3] mux_tree_size14_4_sram;
|
||||
wire [0:3] mux_tree_size14_4_sram_inv;
|
||||
wire [0:0] mux_tree_size14_5_out;
|
||||
wire [0:3] mux_tree_size14_5_sram;
|
||||
wire [0:3] mux_tree_size14_5_sram_inv;
|
||||
wire [0:0] mux_tree_size14_6_out;
|
||||
wire [0:3] mux_tree_size14_6_sram;
|
||||
wire [0:3] mux_tree_size14_6_sram_inv;
|
||||
wire [0:0] mux_tree_size14_7_out;
|
||||
wire [0:3] mux_tree_size14_7_sram;
|
||||
wire [0:3] mux_tree_size14_7_sram_inv;
|
||||
wire [0:0] mux_tree_size14_8_out;
|
||||
wire [0:3] mux_tree_size14_8_sram;
|
||||
wire [0:3] mux_tree_size14_8_sram_inv;
|
||||
wire [0:0] mux_tree_size14_9_out;
|
||||
wire [0:3] mux_tree_size14_9_sram;
|
||||
wire [0:3] mux_tree_size14_9_sram_inv;
|
||||
wire [0:0] mux_tree_size14_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_size14_mem_10_ccff_tail;
|
||||
wire [0:0] mux_tree_size14_mem_11_ccff_tail;
|
||||
wire [0:0] mux_tree_size14_mem_12_ccff_tail;
|
||||
wire [0:0] mux_tree_size14_mem_13_ccff_tail;
|
||||
wire [0:0] mux_tree_size14_mem_14_ccff_tail;
|
||||
wire [0:0] mux_tree_size14_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_size14_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_size14_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_size14_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_size14_mem_5_ccff_tail;
|
||||
wire [0:0] mux_tree_size14_mem_6_ccff_tail;
|
||||
wire [0:0] mux_tree_size14_mem_7_ccff_tail;
|
||||
wire [0:0] mux_tree_size14_mem_8_ccff_tail;
|
||||
wire [0:0] mux_tree_size14_mem_9_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.fle_in({mux_tree_size14_0_out, mux_tree_size14_1_out, mux_tree_size14_2_out, mux_tree_size14_3_out}),
|
||||
.fle_clk(direct_interc_4_out),
|
||||
.ccff_head(ccff_head),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_0_fle_out),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail));
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.fle_in({mux_tree_size14_4_out, mux_tree_size14_5_out, mux_tree_size14_6_out, mux_tree_size14_7_out}),
|
||||
.fle_clk(direct_interc_5_out),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_1_fle_out),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail));
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.fle_in({mux_tree_size14_8_out, mux_tree_size14_9_out, mux_tree_size14_10_out, mux_tree_size14_11_out}),
|
||||
.fle_clk(direct_interc_6_out),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_2_fle_out),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail));
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 (
|
||||
.prog_clk(prog_clk),
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.fle_in({mux_tree_size14_12_out, mux_tree_size14_13_out, mux_tree_size14_14_out, mux_tree_size14_15_out}),
|
||||
.fle_clk(direct_interc_7_out),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_3_fle_out),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail));
|
||||
|
||||
direct_interc direct_interc_0_ (
|
||||
.in(logical_tile_clb_mode_default__fle_0_fle_out),
|
||||
.out(clb_O[0]));
|
||||
|
||||
direct_interc direct_interc_1_ (
|
||||
.in(logical_tile_clb_mode_default__fle_1_fle_out),
|
||||
.out(clb_O[1]));
|
||||
|
||||
direct_interc direct_interc_2_ (
|
||||
.in(logical_tile_clb_mode_default__fle_2_fle_out),
|
||||
.out(clb_O[2]));
|
||||
|
||||
direct_interc direct_interc_3_ (
|
||||
.in(logical_tile_clb_mode_default__fle_3_fle_out),
|
||||
.out(clb_O[3]));
|
||||
|
||||
direct_interc direct_interc_4_ (
|
||||
.in(clb_clk),
|
||||
.out(direct_interc_4_out));
|
||||
|
||||
direct_interc direct_interc_5_ (
|
||||
.in(clb_clk),
|
||||
.out(direct_interc_5_out));
|
||||
|
||||
direct_interc direct_interc_6_ (
|
||||
.in(clb_clk),
|
||||
.out(direct_interc_6_out));
|
||||
|
||||
direct_interc direct_interc_7_ (
|
||||
.in(clb_clk),
|
||||
.out(direct_interc_7_out));
|
||||
|
||||
mux_tree_size14 mux_fle_0_in_0 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_0_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_0_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_0_out));
|
||||
|
||||
mux_tree_size14 mux_fle_0_in_1 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_1_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_1_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_1_out));
|
||||
|
||||
mux_tree_size14 mux_fle_0_in_2 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_2_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_2_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_2_out));
|
||||
|
||||
mux_tree_size14 mux_fle_0_in_3 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_3_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_3_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_3_out));
|
||||
|
||||
mux_tree_size14 mux_fle_1_in_0 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_4_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_4_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_4_out));
|
||||
|
||||
mux_tree_size14 mux_fle_1_in_1 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_5_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_5_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_5_out));
|
||||
|
||||
mux_tree_size14 mux_fle_1_in_2 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_6_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_6_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_6_out));
|
||||
|
||||
mux_tree_size14 mux_fle_1_in_3 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_7_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_7_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_7_out));
|
||||
|
||||
mux_tree_size14 mux_fle_2_in_0 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_8_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_8_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_8_out));
|
||||
|
||||
mux_tree_size14 mux_fle_2_in_1 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_9_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_9_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_9_out));
|
||||
|
||||
mux_tree_size14 mux_fle_2_in_2 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_10_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_10_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_10_out));
|
||||
|
||||
mux_tree_size14 mux_fle_2_in_3 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_11_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_11_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_11_out));
|
||||
|
||||
mux_tree_size14 mux_fle_3_in_0 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_12_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_12_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_12_out));
|
||||
|
||||
mux_tree_size14 mux_fle_3_in_1 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_13_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_13_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_13_out));
|
||||
|
||||
mux_tree_size14 mux_fle_3_in_2 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_14_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_14_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_14_out));
|
||||
|
||||
mux_tree_size14 mux_fle_3_in_3 (
|
||||
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
|
||||
.sram(mux_tree_size14_15_sram[0:3]),
|
||||
.sram_inv(mux_tree_size14_15_sram_inv[0:3]),
|
||||
.out(mux_tree_size14_15_out));
|
||||
|
||||
mux_tree_size14_mem mem_fle_0_in_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_size14_0_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_0_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_0_in_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_size14_1_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_1_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_0_in_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_size14_2_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_2_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_0_in_3 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_size14_3_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_3_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_1_in_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_size14_4_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_4_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_1_in_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_size14_5_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_5_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_1_in_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_5_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_6_ccff_tail),
|
||||
.mem_out(mux_tree_size14_6_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_6_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_1_in_3 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_6_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_7_ccff_tail),
|
||||
.mem_out(mux_tree_size14_7_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_7_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_2_in_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_7_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_8_ccff_tail),
|
||||
.mem_out(mux_tree_size14_8_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_8_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_2_in_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_8_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_9_ccff_tail),
|
||||
.mem_out(mux_tree_size14_9_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_9_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_2_in_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_9_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_10_ccff_tail),
|
||||
.mem_out(mux_tree_size14_10_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_10_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_2_in_3 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_10_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_11_ccff_tail),
|
||||
.mem_out(mux_tree_size14_11_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_11_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_3_in_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_11_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_12_ccff_tail),
|
||||
.mem_out(mux_tree_size14_12_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_12_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_3_in_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_12_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_13_ccff_tail),
|
||||
.mem_out(mux_tree_size14_13_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_13_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_3_in_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_13_ccff_tail),
|
||||
.ccff_tail(mux_tree_size14_mem_14_ccff_tail),
|
||||
.mem_out(mux_tree_size14_14_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_14_sram_inv[0:3]));
|
||||
|
||||
mux_tree_size14_mem mem_fle_3_in_3 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_size14_mem_14_ccff_tail),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(mux_tree_size14_15_sram[0:3]),
|
||||
.mem_outb(mux_tree_size14_15_sram_inv[0:3]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_clb_mode_clb_ -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Physical programmable logic block Verilog module: clb -----
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for pb_type: fle
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Physical programmable logic block Verilog module: fle -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_clb_mode_default__fle -----
|
||||
module logical_tile_clb_mode_default__fle(prog_clk,
|
||||
set,
|
||||
reset,
|
||||
clk,
|
||||
fle_in,
|
||||
fle_clk,
|
||||
ccff_head,
|
||||
fle_out,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] set;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] reset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:3] fle_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] fle_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] fle_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:3] fle_in;
|
||||
wire [0:0] fle_clk;
|
||||
wire [0:0] fle_out;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] direct_interc_1_out;
|
||||
wire [0:0] direct_interc_2_out;
|
||||
wire [0:0] direct_interc_3_out;
|
||||
wire [0:0] direct_interc_4_out;
|
||||
wire [0:0] direct_interc_5_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0_ble4_out;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.ble4_in({direct_interc_1_out, direct_interc_2_out, direct_interc_3_out, direct_interc_4_out}),
|
||||
.ble4_clk(direct_interc_5_out),
|
||||
.ccff_head(ccff_head),
|
||||
.ble4_out(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0_ble4_out),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
direct_interc direct_interc_0_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0_ble4_out),
|
||||
.out(fle_out));
|
||||
|
||||
direct_interc direct_interc_1_ (
|
||||
.in(fle_in[0]),
|
||||
.out(direct_interc_1_out));
|
||||
|
||||
direct_interc direct_interc_2_ (
|
||||
.in(fle_in[1]),
|
||||
.out(direct_interc_2_out));
|
||||
|
||||
direct_interc direct_interc_3_ (
|
||||
.in(fle_in[2]),
|
||||
.out(direct_interc_3_out));
|
||||
|
||||
direct_interc direct_interc_4_ (
|
||||
.in(fle_in[3]),
|
||||
.out(direct_interc_4_out));
|
||||
|
||||
direct_interc direct_interc_5_ (
|
||||
.in(fle_clk),
|
||||
.out(direct_interc_5_out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_clb_mode_default__fle -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Physical programmable logic block Verilog module: fle -----
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for pb_type: ble4
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Physical programmable logic block Verilog module: ble4 -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 -----
|
||||
module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4(prog_clk,
|
||||
set,
|
||||
reset,
|
||||
clk,
|
||||
ble4_in,
|
||||
ble4_clk,
|
||||
ccff_head,
|
||||
ble4_out,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] set;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] reset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:3] ble4_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ble4_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ble4_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:3] ble4_in;
|
||||
wire [0:0] ble4_clk;
|
||||
wire [0:0] ble4_out;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] direct_interc_0_out;
|
||||
wire [0:0] direct_interc_1_out;
|
||||
wire [0:0] direct_interc_2_out;
|
||||
wire [0:0] direct_interc_3_out;
|
||||
wire [0:0] direct_interc_4_out;
|
||||
wire [0:0] direct_interc_5_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0_ff_Q;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.lut4_in({direct_interc_0_out, direct_interc_1_out, direct_interc_2_out, direct_interc_3_out}),
|
||||
.ccff_head(ccff_head),
|
||||
.lut4_out(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_ccff_tail));
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0 (
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.ff_D(direct_interc_4_out),
|
||||
.ff_Q(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0_ff_Q),
|
||||
.ff_clk(direct_interc_5_out));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_ble4_out_0 (
|
||||
.in({logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0_ff_Q, logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out}),
|
||||
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
|
||||
.out(ble4_out));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_ble4_out_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_ccff_tail),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
|
||||
|
||||
direct_interc direct_interc_0_ (
|
||||
.in(ble4_in[0]),
|
||||
.out(direct_interc_0_out));
|
||||
|
||||
direct_interc direct_interc_1_ (
|
||||
.in(ble4_in[1]),
|
||||
.out(direct_interc_1_out));
|
||||
|
||||
direct_interc direct_interc_2_ (
|
||||
.in(ble4_in[2]),
|
||||
.out(direct_interc_2_out));
|
||||
|
||||
direct_interc direct_interc_3_ (
|
||||
.in(ble4_in[3]),
|
||||
.out(direct_interc_3_out));
|
||||
|
||||
direct_interc direct_interc_4_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out),
|
||||
.out(direct_interc_4_out));
|
||||
|
||||
direct_interc direct_interc_5_ (
|
||||
.in(ble4_clk),
|
||||
.out(direct_interc_5_out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Physical programmable logic block Verilog module: ble4 -----
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for primitive pb_type: ff
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff -----
|
||||
module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff(set,
|
||||
reset,
|
||||
clk,
|
||||
ff_D,
|
||||
ff_Q,
|
||||
ff_clk);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] set;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] reset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ff_D;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ff_Q;
|
||||
//----- CLOCK PORTS -----
|
||||
input [0:0] ff_clk;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:0] ff_D;
|
||||
wire [0:0] ff_Q;
|
||||
wire [0:0] ff_clk;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
DFFSRQ DFFSRQ_0_ (
|
||||
.SET(set),
|
||||
.RST(reset),
|
||||
.CK(clk),
|
||||
.D(ff_D),
|
||||
.Q(ff_Q));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for primitive pb_type: lut4
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 -----
|
||||
module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4(prog_clk,
|
||||
lut4_in,
|
||||
ccff_head,
|
||||
lut4_out,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:3] lut4_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] lut4_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:3] lut4_in;
|
||||
wire [0:0] lut4_out;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:15] lut4_0_sram;
|
||||
wire [0:15] lut4_0_sram_inv;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
lut4 lut4_0_ (
|
||||
.in(lut4_in[0:3]),
|
||||
.sram(lut4_0_sram[0:15]),
|
||||
.sram_inv(lut4_0_sram_inv[0:15]),
|
||||
.out(lut4_out));
|
||||
|
||||
lut4_DFF_mem lut4_DFF_mem (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(ccff_head),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(lut4_0_sram[0:15]),
|
||||
.mem_outb(lut4_0_sram_inv[0:15]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for pb_type: io
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Physical programmable logic block Verilog module: io -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_io_mode_io_ -----
|
||||
module logical_tile_io_mode_io_(prog_clk,
|
||||
gfpga_pad_GPIO_PAD,
|
||||
io_outpad,
|
||||
ccff_head,
|
||||
io_inpad,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:0] gfpga_pad_GPIO_PAD;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] io_outpad;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] io_inpad;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:0] io_outpad;
|
||||
wire [0:0] io_inpad;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] direct_interc_1_out;
|
||||
wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD),
|
||||
.iopad_outpad(direct_interc_1_out),
|
||||
.ccff_head(ccff_head),
|
||||
.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
direct_interc direct_interc_0_ (
|
||||
.in(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
|
||||
.out(io_inpad));
|
||||
|
||||
direct_interc direct_interc_1_ (
|
||||
.in(io_outpad),
|
||||
.out(direct_interc_1_out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_io_mode_io_ -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Physical programmable logic block Verilog module: io -----
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for primitive pb_type: iopad
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_io_mode_physical__iopad -----
|
||||
module logical_tile_io_mode_physical__iopad(prog_clk,
|
||||
gfpga_pad_GPIO_PAD,
|
||||
iopad_outpad,
|
||||
ccff_head,
|
||||
iopad_inpad,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:0] gfpga_pad_GPIO_PAD;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] iopad_outpad;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] iopad_inpad;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:0] iopad_outpad;
|
||||
wire [0:0] iopad_inpad;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] GPIO_0_DIR;
|
||||
wire [0:0] GPIO_DFF_mem_undriven_mem_outb;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
GPIO GPIO_0_ (
|
||||
.PAD(gfpga_pad_GPIO_PAD),
|
||||
.A(iopad_outpad),
|
||||
.DIR(GPIO_0_DIR),
|
||||
.Y(iopad_inpad));
|
||||
|
||||
GPIO_DFF_mem GPIO_DFF_mem (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(ccff_head),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(GPIO_0_DIR),
|
||||
.mem_outb(GPIO_DFF_mem_undriven_mem_outb));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_io_mode_physical__iopad -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,237 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] 2.500000033e-11
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10
|
||||
set_min_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10
|
||||
set_min_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10
|
||||
set_min_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10
|
||||
set_min_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/grid_io_left/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left/logical_tile_io_mode_io__0/io_inpad[0] 4.243000049e-11
|
||||
set_max_delay -from fpga_top/grid_io_left/logical_tile_io_mode_io__0/io_outpad[0] -to fpga_top/grid_io_left/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
<!--
|
||||
- I/O mapping
|
||||
- Version: 1.0.3764-dev+dd400579-dirty
|
||||
-->
|
||||
|
||||
<io_mapping>
|
||||
<io name="gfpga_pad_GPIO_PAD[6:6]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[1:1]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[9:9]" net="c" dir="output"/>
|
||||
</io_mapping>
|
||||
|
|
@ -0,0 +1,370 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for Unique Connection Blocks[1][0]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for cbx_1__0_ -----
|
||||
module cbx_1__0_(prog_clk,
|
||||
chanx_left_in,
|
||||
chanx_right_in,
|
||||
ccff_head,
|
||||
chanx_left_out,
|
||||
chanx_right_out,
|
||||
top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_,
|
||||
top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_,
|
||||
top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_,
|
||||
bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_,
|
||||
bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_,
|
||||
bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_,
|
||||
bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_,
|
||||
bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_,
|
||||
bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_,
|
||||
bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_,
|
||||
bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chanx_left_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chanx_right_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chanx_left_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chanx_right_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:2] mux_tree_tapbuf_size6_0_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_10_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_10_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_1_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_2_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_2_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_3_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_3_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_4_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_4_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_5_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_5_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_6_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_6_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_7_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_7_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_8_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_8_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_9_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_9_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- Local connection due to Wire 0 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[0] = chanx_left_in[0];
|
||||
// ----- Local connection due to Wire 1 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[1] = chanx_left_in[1];
|
||||
// ----- Local connection due to Wire 2 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[2] = chanx_left_in[2];
|
||||
// ----- Local connection due to Wire 3 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[3] = chanx_left_in[3];
|
||||
// ----- Local connection due to Wire 4 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[4] = chanx_left_in[4];
|
||||
// ----- Local connection due to Wire 5 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[5] = chanx_left_in[5];
|
||||
// ----- Local connection due to Wire 6 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[6] = chanx_left_in[6];
|
||||
// ----- Local connection due to Wire 7 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[7] = chanx_left_in[7];
|
||||
// ----- Local connection due to Wire 8 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[8] = chanx_left_in[8];
|
||||
// ----- Local connection due to Wire 9 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[9] = chanx_left_in[9];
|
||||
// ----- Local connection due to Wire 10 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[10] = chanx_left_in[10];
|
||||
// ----- Local connection due to Wire 11 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[11] = chanx_left_in[11];
|
||||
// ----- Local connection due to Wire 12 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[12] = chanx_left_in[12];
|
||||
// ----- Local connection due to Wire 13 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[0] = chanx_right_in[0];
|
||||
// ----- Local connection due to Wire 14 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[1] = chanx_right_in[1];
|
||||
// ----- Local connection due to Wire 15 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[2] = chanx_right_in[2];
|
||||
// ----- Local connection due to Wire 16 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[3] = chanx_right_in[3];
|
||||
// ----- Local connection due to Wire 17 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[4] = chanx_right_in[4];
|
||||
// ----- Local connection due to Wire 18 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[5] = chanx_right_in[5];
|
||||
// ----- Local connection due to Wire 19 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[6] = chanx_right_in[6];
|
||||
// ----- Local connection due to Wire 20 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[7] = chanx_right_in[7];
|
||||
// ----- Local connection due to Wire 21 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[8] = chanx_right_in[8];
|
||||
// ----- Local connection due to Wire 22 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[9] = chanx_right_in[9];
|
||||
// ----- Local connection due to Wire 23 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[10] = chanx_right_in[10];
|
||||
// ----- Local connection due to Wire 24 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[11] = chanx_right_in[11];
|
||||
// ----- Local connection due to Wire 25 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[12] = chanx_right_in[12];
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
mux_tree_tapbuf_size6 mux_bottom_ipin_0 (
|
||||
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}),
|
||||
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
|
||||
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_bottom_ipin_1 (
|
||||
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7]}),
|
||||
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
|
||||
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_bottom_ipin_2 (
|
||||
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8]}),
|
||||
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]),
|
||||
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_top_ipin_0 (
|
||||
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9]}),
|
||||
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]),
|
||||
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_top_ipin_1 (
|
||||
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10]}),
|
||||
.sram(mux_tree_tapbuf_size6_4_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]),
|
||||
.out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_top_ipin_2 (
|
||||
.in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11]}),
|
||||
.sram(mux_tree_tapbuf_size6_5_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]),
|
||||
.out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_top_ipin_3 (
|
||||
.in({chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}),
|
||||
.sram(mux_tree_tapbuf_size6_6_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]),
|
||||
.out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_top_ipin_4 (
|
||||
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}),
|
||||
.sram(mux_tree_tapbuf_size6_7_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]),
|
||||
.out(bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_top_ipin_5 (
|
||||
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7], chanx_left_in[8], chanx_right_in[8]}),
|
||||
.sram(mux_tree_tapbuf_size6_8_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]),
|
||||
.out(bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_top_ipin_6 (
|
||||
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}),
|
||||
.sram(mux_tree_tapbuf_size6_9_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]),
|
||||
.out(bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_top_ipin_7 (
|
||||
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[10], chanx_right_in[10]}),
|
||||
.sram(mux_tree_tapbuf_size6_10_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_10_sram_inv[0:2]),
|
||||
.out(bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_bottom_ipin_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(ccff_head),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_bottom_ipin_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_bottom_ipin_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_top_ipin_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_top_ipin_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_top_ipin_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_top_ipin_3 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_top_ipin_4 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_7_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_top_ipin_5 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_8_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_top_ipin_6 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_9_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_top_ipin_7 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_10_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_10_sram_inv[0:2]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for cbx_1__0_ -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,370 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for Unique Connection Blocks[1][1]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for cbx_1__1_ -----
|
||||
module cbx_1__1_(prog_clk,
|
||||
chanx_left_in,
|
||||
chanx_right_in,
|
||||
ccff_head,
|
||||
chanx_left_out,
|
||||
chanx_right_out,
|
||||
top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_,
|
||||
top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_,
|
||||
top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_,
|
||||
top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_,
|
||||
top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_,
|
||||
top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_,
|
||||
top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_,
|
||||
top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_,
|
||||
bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_,
|
||||
bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_,
|
||||
bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chanx_left_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chanx_right_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chanx_left_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chanx_right_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:2] mux_tree_tapbuf_size6_0_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_10_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_10_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_1_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_2_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_2_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_3_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_3_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_4_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_4_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_5_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_5_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_6_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_6_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_7_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_7_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_8_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_8_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_9_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_9_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- Local connection due to Wire 0 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[0] = chanx_left_in[0];
|
||||
// ----- Local connection due to Wire 1 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[1] = chanx_left_in[1];
|
||||
// ----- Local connection due to Wire 2 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[2] = chanx_left_in[2];
|
||||
// ----- Local connection due to Wire 3 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[3] = chanx_left_in[3];
|
||||
// ----- Local connection due to Wire 4 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[4] = chanx_left_in[4];
|
||||
// ----- Local connection due to Wire 5 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[5] = chanx_left_in[5];
|
||||
// ----- Local connection due to Wire 6 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[6] = chanx_left_in[6];
|
||||
// ----- Local connection due to Wire 7 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[7] = chanx_left_in[7];
|
||||
// ----- Local connection due to Wire 8 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[8] = chanx_left_in[8];
|
||||
// ----- Local connection due to Wire 9 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[9] = chanx_left_in[9];
|
||||
// ----- Local connection due to Wire 10 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[10] = chanx_left_in[10];
|
||||
// ----- Local connection due to Wire 11 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[11] = chanx_left_in[11];
|
||||
// ----- Local connection due to Wire 12 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_right_out[12] = chanx_left_in[12];
|
||||
// ----- Local connection due to Wire 13 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[0] = chanx_right_in[0];
|
||||
// ----- Local connection due to Wire 14 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[1] = chanx_right_in[1];
|
||||
// ----- Local connection due to Wire 15 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[2] = chanx_right_in[2];
|
||||
// ----- Local connection due to Wire 16 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[3] = chanx_right_in[3];
|
||||
// ----- Local connection due to Wire 17 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[4] = chanx_right_in[4];
|
||||
// ----- Local connection due to Wire 18 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[5] = chanx_right_in[5];
|
||||
// ----- Local connection due to Wire 19 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[6] = chanx_right_in[6];
|
||||
// ----- Local connection due to Wire 20 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[7] = chanx_right_in[7];
|
||||
// ----- Local connection due to Wire 21 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[8] = chanx_right_in[8];
|
||||
// ----- Local connection due to Wire 22 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[9] = chanx_right_in[9];
|
||||
// ----- Local connection due to Wire 23 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[10] = chanx_right_in[10];
|
||||
// ----- Local connection due to Wire 24 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[11] = chanx_right_in[11];
|
||||
// ----- Local connection due to Wire 25 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chanx_left_out[12] = chanx_right_in[12];
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
mux_tree_tapbuf_size6 mux_bottom_ipin_0 (
|
||||
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}),
|
||||
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
|
||||
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_bottom_ipin_1 (
|
||||
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7]}),
|
||||
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
|
||||
.out(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_bottom_ipin_2 (
|
||||
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8]}),
|
||||
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]),
|
||||
.out(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_bottom_ipin_3 (
|
||||
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9]}),
|
||||
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]),
|
||||
.out(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_bottom_ipin_4 (
|
||||
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10]}),
|
||||
.sram(mux_tree_tapbuf_size6_4_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]),
|
||||
.out(top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_bottom_ipin_5 (
|
||||
.in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11]}),
|
||||
.sram(mux_tree_tapbuf_size6_5_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]),
|
||||
.out(top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_bottom_ipin_6 (
|
||||
.in({chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}),
|
||||
.sram(mux_tree_tapbuf_size6_6_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]),
|
||||
.out(top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_bottom_ipin_7 (
|
||||
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}),
|
||||
.sram(mux_tree_tapbuf_size6_7_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]),
|
||||
.out(top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_top_ipin_0 (
|
||||
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7], chanx_left_in[8], chanx_right_in[8]}),
|
||||
.sram(mux_tree_tapbuf_size6_8_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]),
|
||||
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_top_ipin_1 (
|
||||
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}),
|
||||
.sram(mux_tree_tapbuf_size6_9_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]),
|
||||
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_top_ipin_2 (
|
||||
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[10], chanx_right_in[10]}),
|
||||
.sram(mux_tree_tapbuf_size6_10_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_10_sram_inv[0:2]),
|
||||
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_bottom_ipin_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(ccff_head),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_bottom_ipin_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_bottom_ipin_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_bottom_ipin_3 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_bottom_ipin_4 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_bottom_ipin_5 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_bottom_ipin_6 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_bottom_ipin_7 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_7_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_top_ipin_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_8_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_top_ipin_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_9_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_top_ipin_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_10_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_10_sram_inv[0:2]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for cbx_1__1_ -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,351 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for Unique Connection Blocks[0][1]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for cby_0__1_ -----
|
||||
module cby_0__1_(prog_clk,
|
||||
chany_bottom_in,
|
||||
chany_top_in,
|
||||
ccff_head,
|
||||
chany_bottom_out,
|
||||
chany_top_out,
|
||||
right_grid_left_width_0_height_0_subtile_0__pin_I_3_,
|
||||
right_grid_left_width_0_height_0_subtile_0__pin_I_7_,
|
||||
left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_,
|
||||
left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_,
|
||||
left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_,
|
||||
left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_,
|
||||
left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_,
|
||||
left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_,
|
||||
left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_,
|
||||
left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chany_bottom_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chany_top_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chany_bottom_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chany_top_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_3_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_7_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:2] mux_tree_tapbuf_size6_0_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_1_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_2_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_2_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_3_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_3_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_4_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_4_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_5_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_5_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_6_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_6_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_7_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_7_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_8_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_8_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_9_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_9_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- Local connection due to Wire 0 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[0] = chany_bottom_in[0];
|
||||
// ----- Local connection due to Wire 1 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[1] = chany_bottom_in[1];
|
||||
// ----- Local connection due to Wire 2 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[2] = chany_bottom_in[2];
|
||||
// ----- Local connection due to Wire 3 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[3] = chany_bottom_in[3];
|
||||
// ----- Local connection due to Wire 4 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[4] = chany_bottom_in[4];
|
||||
// ----- Local connection due to Wire 5 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[5] = chany_bottom_in[5];
|
||||
// ----- Local connection due to Wire 6 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[6] = chany_bottom_in[6];
|
||||
// ----- Local connection due to Wire 7 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[7] = chany_bottom_in[7];
|
||||
// ----- Local connection due to Wire 8 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[8] = chany_bottom_in[8];
|
||||
// ----- Local connection due to Wire 9 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[9] = chany_bottom_in[9];
|
||||
// ----- Local connection due to Wire 10 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[10] = chany_bottom_in[10];
|
||||
// ----- Local connection due to Wire 11 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[11] = chany_bottom_in[11];
|
||||
// ----- Local connection due to Wire 12 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[12] = chany_bottom_in[12];
|
||||
// ----- Local connection due to Wire 13 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[0] = chany_top_in[0];
|
||||
// ----- Local connection due to Wire 14 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[1] = chany_top_in[1];
|
||||
// ----- Local connection due to Wire 15 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[2] = chany_top_in[2];
|
||||
// ----- Local connection due to Wire 16 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[3] = chany_top_in[3];
|
||||
// ----- Local connection due to Wire 17 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[4] = chany_top_in[4];
|
||||
// ----- Local connection due to Wire 18 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[5] = chany_top_in[5];
|
||||
// ----- Local connection due to Wire 19 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[6] = chany_top_in[6];
|
||||
// ----- Local connection due to Wire 20 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[7] = chany_top_in[7];
|
||||
// ----- Local connection due to Wire 21 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[8] = chany_top_in[8];
|
||||
// ----- Local connection due to Wire 22 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[9] = chany_top_in[9];
|
||||
// ----- Local connection due to Wire 23 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[10] = chany_top_in[10];
|
||||
// ----- Local connection due to Wire 24 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[11] = chany_top_in[11];
|
||||
// ----- Local connection due to Wire 25 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[12] = chany_top_in[12];
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
mux_tree_tapbuf_size6 mux_left_ipin_0 (
|
||||
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}),
|
||||
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
|
||||
.out(right_grid_left_width_0_height_0_subtile_0__pin_I_3_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_left_ipin_1 (
|
||||
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7]}),
|
||||
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
|
||||
.out(right_grid_left_width_0_height_0_subtile_0__pin_I_7_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_right_ipin_0 (
|
||||
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8]}),
|
||||
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]),
|
||||
.out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_right_ipin_1 (
|
||||
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9]}),
|
||||
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]),
|
||||
.out(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_right_ipin_2 (
|
||||
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10]}),
|
||||
.sram(mux_tree_tapbuf_size6_4_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]),
|
||||
.out(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_right_ipin_3 (
|
||||
.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11]}),
|
||||
.sram(mux_tree_tapbuf_size6_5_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]),
|
||||
.out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_right_ipin_4 (
|
||||
.in({chany_bottom_in[5], chany_top_in[5], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}),
|
||||
.sram(mux_tree_tapbuf_size6_6_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]),
|
||||
.out(left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_right_ipin_5 (
|
||||
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[7], chany_top_in[7]}),
|
||||
.sram(mux_tree_tapbuf_size6_7_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]),
|
||||
.out(left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_right_ipin_6 (
|
||||
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[8], chany_top_in[8]}),
|
||||
.sram(mux_tree_tapbuf_size6_8_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]),
|
||||
.out(left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_right_ipin_7 (
|
||||
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[9], chany_top_in[9]}),
|
||||
.sram(mux_tree_tapbuf_size6_9_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]),
|
||||
.out(left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_left_ipin_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(ccff_head),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_left_ipin_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_right_ipin_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_right_ipin_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_right_ipin_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_right_ipin_3 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_right_ipin_4 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_right_ipin_5 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_7_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_right_ipin_6 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_8_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_right_ipin_7 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_9_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for cby_0__1_ -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,370 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for Unique Connection Blocks[1][1]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for cby_1__1_ -----
|
||||
module cby_1__1_(prog_clk,
|
||||
chany_bottom_in,
|
||||
chany_top_in,
|
||||
ccff_head,
|
||||
chany_bottom_out,
|
||||
chany_top_out,
|
||||
right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_,
|
||||
right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_,
|
||||
right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_,
|
||||
right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_,
|
||||
right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_,
|
||||
right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_,
|
||||
right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_,
|
||||
right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_,
|
||||
left_grid_right_width_0_height_0_subtile_0__pin_I_1_,
|
||||
left_grid_right_width_0_height_0_subtile_0__pin_I_5_,
|
||||
left_grid_right_width_0_height_0_subtile_0__pin_I_9_,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chany_bottom_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chany_top_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chany_bottom_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chany_top_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_1_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_5_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_9_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:2] mux_tree_tapbuf_size6_0_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_10_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_10_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_1_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_2_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_2_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_3_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_3_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_4_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_4_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_5_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_5_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_6_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_6_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_7_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_7_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_8_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_8_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size6_9_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size6_9_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- Local connection due to Wire 0 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[0] = chany_bottom_in[0];
|
||||
// ----- Local connection due to Wire 1 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[1] = chany_bottom_in[1];
|
||||
// ----- Local connection due to Wire 2 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[2] = chany_bottom_in[2];
|
||||
// ----- Local connection due to Wire 3 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[3] = chany_bottom_in[3];
|
||||
// ----- Local connection due to Wire 4 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[4] = chany_bottom_in[4];
|
||||
// ----- Local connection due to Wire 5 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[5] = chany_bottom_in[5];
|
||||
// ----- Local connection due to Wire 6 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[6] = chany_bottom_in[6];
|
||||
// ----- Local connection due to Wire 7 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[7] = chany_bottom_in[7];
|
||||
// ----- Local connection due to Wire 8 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[8] = chany_bottom_in[8];
|
||||
// ----- Local connection due to Wire 9 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[9] = chany_bottom_in[9];
|
||||
// ----- Local connection due to Wire 10 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[10] = chany_bottom_in[10];
|
||||
// ----- Local connection due to Wire 11 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[11] = chany_bottom_in[11];
|
||||
// ----- Local connection due to Wire 12 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_top_out[12] = chany_bottom_in[12];
|
||||
// ----- Local connection due to Wire 13 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[0] = chany_top_in[0];
|
||||
// ----- Local connection due to Wire 14 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[1] = chany_top_in[1];
|
||||
// ----- Local connection due to Wire 15 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[2] = chany_top_in[2];
|
||||
// ----- Local connection due to Wire 16 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[3] = chany_top_in[3];
|
||||
// ----- Local connection due to Wire 17 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[4] = chany_top_in[4];
|
||||
// ----- Local connection due to Wire 18 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[5] = chany_top_in[5];
|
||||
// ----- Local connection due to Wire 19 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[6] = chany_top_in[6];
|
||||
// ----- Local connection due to Wire 20 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[7] = chany_top_in[7];
|
||||
// ----- Local connection due to Wire 21 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[8] = chany_top_in[8];
|
||||
// ----- Local connection due to Wire 22 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[9] = chany_top_in[9];
|
||||
// ----- Local connection due to Wire 23 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[10] = chany_top_in[10];
|
||||
// ----- Local connection due to Wire 24 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[11] = chany_top_in[11];
|
||||
// ----- Local connection due to Wire 25 -----
|
||||
// ----- Net source id 0 -----
|
||||
// ----- Net sink id 0 -----
|
||||
assign chany_bottom_out[12] = chany_top_in[12];
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
mux_tree_tapbuf_size6 mux_left_ipin_0 (
|
||||
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}),
|
||||
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
|
||||
.out(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_left_ipin_1 (
|
||||
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7]}),
|
||||
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
|
||||
.out(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_left_ipin_2 (
|
||||
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8]}),
|
||||
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]),
|
||||
.out(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_left_ipin_3 (
|
||||
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9]}),
|
||||
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]),
|
||||
.out(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_left_ipin_4 (
|
||||
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10]}),
|
||||
.sram(mux_tree_tapbuf_size6_4_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]),
|
||||
.out(right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_left_ipin_5 (
|
||||
.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11]}),
|
||||
.sram(mux_tree_tapbuf_size6_5_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]),
|
||||
.out(right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_left_ipin_6 (
|
||||
.in({chany_bottom_in[5], chany_top_in[5], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}),
|
||||
.sram(mux_tree_tapbuf_size6_6_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]),
|
||||
.out(right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_left_ipin_7 (
|
||||
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[7], chany_top_in[7]}),
|
||||
.sram(mux_tree_tapbuf_size6_7_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]),
|
||||
.out(right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_right_ipin_0 (
|
||||
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[8], chany_top_in[8]}),
|
||||
.sram(mux_tree_tapbuf_size6_8_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]),
|
||||
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_1_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_right_ipin_1 (
|
||||
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[9], chany_top_in[9]}),
|
||||
.sram(mux_tree_tapbuf_size6_9_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]),
|
||||
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_5_));
|
||||
|
||||
mux_tree_tapbuf_size6 mux_right_ipin_2 (
|
||||
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[10], chany_top_in[10]}),
|
||||
.sram(mux_tree_tapbuf_size6_10_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size6_10_sram_inv[0:2]),
|
||||
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_9_));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_left_ipin_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(ccff_head),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_left_ipin_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_left_ipin_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_left_ipin_3 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_left_ipin_4 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_left_ipin_5 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_left_ipin_6 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_left_ipin_7 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_7_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_right_ipin_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_8_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_right_ipin_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_9_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size6_mem mem_right_ipin_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size6_10_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size6_10_sram_inv[0:2]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for cby_1__1_ -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,526 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for Unique Switch Blocks[0][0]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for sb_0__0_ -----
|
||||
module sb_0__0_(prog_clk,
|
||||
chany_top_in,
|
||||
top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_,
|
||||
chanx_right_in,
|
||||
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_,
|
||||
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
ccff_head,
|
||||
chany_top_out,
|
||||
chanx_right_out,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chany_top_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chanx_right_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chany_top_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chanx_right_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_1_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_2_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_3_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_4_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_5_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
|
||||
wire [0:1] mux_tree_tapbuf_size3_0_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_10_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_10_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_11_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_11_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_12_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_12_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_13_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_13_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_1_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_2_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_2_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_3_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_3_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_4_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_4_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_5_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_5_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_6_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_6_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_7_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_7_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_8_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_8_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_9_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_9_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail;
|
||||
wire [0:2] mux_tree_tapbuf_size4_0_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_1_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_2_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_3_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_4_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_4_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_5_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_5_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
mux_tree_tapbuf_size4 mux_top_track_0 (
|
||||
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[1]}),
|
||||
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
|
||||
.out(chany_top_out[0]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_top_track_12 (
|
||||
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[7]}),
|
||||
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
|
||||
.out(chany_top_out[6]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_right_track_0 (
|
||||
.in({chany_top_in[12], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
|
||||
.out(chanx_right_out[0]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_right_track_2 (
|
||||
.in({chany_top_in[0], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
|
||||
.out(chanx_right_out[1]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_right_track_12 (
|
||||
.in({chany_top_in[5], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size4_4_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]),
|
||||
.out(chanx_right_out[6]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_right_track_14 (
|
||||
.in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size4_5_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]),
|
||||
.out(chanx_right_out[7]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_top_track_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(ccff_head),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_top_track_12 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_right_track_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_right_track_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_right_track_12 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_right_track_14 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_5_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_top_track_2 (
|
||||
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[2]}),
|
||||
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
|
||||
.out(chany_top_out[1]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_top_track_4 (
|
||||
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[3]}),
|
||||
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
|
||||
.out(chany_top_out[2]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_top_track_6 (
|
||||
.in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, chanx_right_in[4]}),
|
||||
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]),
|
||||
.out(chany_top_out[3]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_top_track_8 (
|
||||
.in({top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, chanx_right_in[5]}),
|
||||
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]),
|
||||
.out(chany_top_out[4]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_top_track_10 (
|
||||
.in({top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, chanx_right_in[6]}),
|
||||
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]),
|
||||
.out(chany_top_out[5]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_top_track_14 (
|
||||
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[8]}),
|
||||
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]),
|
||||
.out(chany_top_out[7]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_top_track_16 (
|
||||
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, chanx_right_in[9]}),
|
||||
.sram(mux_tree_tapbuf_size3_6_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]),
|
||||
.out(chany_top_out[8]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_top_track_24 (
|
||||
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, chanx_right_in[0]}),
|
||||
.sram(mux_tree_tapbuf_size3_7_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]),
|
||||
.out(chany_top_out[12]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_right_track_4 (
|
||||
.in({chany_top_in[1], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_8_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]),
|
||||
.out(chanx_right_out[2]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_right_track_6 (
|
||||
.in({chany_top_in[2], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_9_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]),
|
||||
.out(chanx_right_out[3]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_right_track_8 (
|
||||
.in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_10_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]),
|
||||
.out(chanx_right_out[4]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_right_track_10 (
|
||||
.in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_11_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]),
|
||||
.out(chanx_right_out[5]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_right_track_16 (
|
||||
.in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_12_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_12_sram_inv[0:1]),
|
||||
.out(chanx_right_out[8]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_right_track_24 (
|
||||
.in({chany_top_in[11], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_13_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_13_sram_inv[0:1]),
|
||||
.out(chanx_right_out[12]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_top_track_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_top_track_4 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_top_track_6 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_top_track_8 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_top_track_10 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_top_track_14 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_top_track_16 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_top_track_24 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_7_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_right_track_4 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_8_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_right_track_6 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_9_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_right_track_8 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_10_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_right_track_10 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_11_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_right_track_16 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_12_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_12_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_right_track_24 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_13_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_13_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_top_track_18 (
|
||||
.in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[10]}),
|
||||
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
|
||||
.out(chany_top_out[9]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_top_track_20 (
|
||||
.in({top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, chanx_right_in[11]}),
|
||||
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
|
||||
.out(chany_top_out[10]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_top_track_22 (
|
||||
.in({top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, chanx_right_in[12]}),
|
||||
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
|
||||
.out(chany_top_out[11]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_right_track_18 (
|
||||
.in({chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
|
||||
.out(chanx_right_out[9]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_right_track_20 (
|
||||
.in({chany_top_in[9], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
|
||||
.out(chanx_right_out[10]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_right_track_22 (
|
||||
.in({chany_top_in[10], right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
|
||||
.out(chanx_right_out[11]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_top_track_18 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_top_track_20 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_top_track_22 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_right_track_18 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_right_track_20 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_right_track_22 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for sb_0__0_ -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,526 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for Unique Switch Blocks[0][1]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for sb_0__1_ -----
|
||||
module sb_0__1_(prog_clk,
|
||||
chanx_right_in,
|
||||
right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
|
||||
chany_bottom_in,
|
||||
bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_,
|
||||
bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
ccff_head,
|
||||
chanx_right_out,
|
||||
chany_bottom_out,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chanx_right_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chany_bottom_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chanx_right_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chany_bottom_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_1_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_2_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_3_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_4_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_5_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_6_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
|
||||
wire [0:1] mux_tree_tapbuf_size3_0_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_10_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_10_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_11_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_11_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_12_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_12_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_13_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_13_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_1_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_2_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_2_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_3_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_3_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_4_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_4_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_5_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_5_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_6_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_6_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_7_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_7_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_8_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_8_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_9_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_9_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_13_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail;
|
||||
wire [0:2] mux_tree_tapbuf_size4_0_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_1_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_2_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_3_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_4_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_4_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
mux_tree_tapbuf_size4 mux_right_track_0 (
|
||||
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[11]}),
|
||||
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
|
||||
.out(chanx_right_out[0]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_right_track_12 (
|
||||
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[5]}),
|
||||
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
|
||||
.out(chanx_right_out[6]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_bottom_track_1 (
|
||||
.in({chanx_right_in[11], bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
|
||||
.out(chany_bottom_out[0]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_bottom_track_3 (
|
||||
.in({chanx_right_in[10], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
|
||||
.out(chany_bottom_out[1]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_bottom_track_15 (
|
||||
.in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size4_4_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]),
|
||||
.out(chany_bottom_out[7]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_right_track_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(ccff_head),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_right_track_12 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_bottom_track_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_bottom_track_3 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_bottom_track_15 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_right_track_2 (
|
||||
.in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[10]}),
|
||||
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
|
||||
.out(chanx_right_out[1]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_right_track_4 (
|
||||
.in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[9]}),
|
||||
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
|
||||
.out(chanx_right_out[2]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_right_track_6 (
|
||||
.in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, chany_bottom_in[8]}),
|
||||
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]),
|
||||
.out(chanx_right_out[3]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_right_track_8 (
|
||||
.in({right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, chany_bottom_in[7]}),
|
||||
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]),
|
||||
.out(chanx_right_out[4]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_right_track_10 (
|
||||
.in({right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, chany_bottom_in[6]}),
|
||||
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]),
|
||||
.out(chanx_right_out[5]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_right_track_14 (
|
||||
.in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[4]}),
|
||||
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]),
|
||||
.out(chanx_right_out[7]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_right_track_16 (
|
||||
.in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[3]}),
|
||||
.sram(mux_tree_tapbuf_size3_6_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]),
|
||||
.out(chanx_right_out[8]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_right_track_24 (
|
||||
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, chany_bottom_in[12]}),
|
||||
.sram(mux_tree_tapbuf_size3_7_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]),
|
||||
.out(chanx_right_out[12]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_bottom_track_5 (
|
||||
.in({chanx_right_in[9], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_8_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[2]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_bottom_track_7 (
|
||||
.in({chanx_right_in[8], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_9_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[3]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_bottom_track_9 (
|
||||
.in({chanx_right_in[7], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_10_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[4]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_bottom_track_11 (
|
||||
.in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_11_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[5]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_bottom_track_13 (
|
||||
.in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_12_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_12_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[6]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_bottom_track_17 (
|
||||
.in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_13_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_13_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[8]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_right_track_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_right_track_4 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_right_track_6 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_right_track_8 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_right_track_10 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_right_track_14 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_right_track_16 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_right_track_24 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_7_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_bottom_track_5 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_8_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_bottom_track_7 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_9_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_bottom_track_9 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_10_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_bottom_track_11 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_11_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_bottom_track_13 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_12_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_12_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_bottom_track_17 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_13_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_13_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_right_track_18 (
|
||||
.in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[2]}),
|
||||
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
|
||||
.out(chanx_right_out[9]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_right_track_20 (
|
||||
.in({right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, chany_bottom_in[1]}),
|
||||
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
|
||||
.out(chanx_right_out[10]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_right_track_22 (
|
||||
.in({right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, chany_bottom_in[0]}),
|
||||
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
|
||||
.out(chanx_right_out[11]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_bottom_track_19 (
|
||||
.in({chanx_right_in[2], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[9]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_bottom_track_21 (
|
||||
.in({chanx_right_in[1], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[10]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_bottom_track_23 (
|
||||
.in({chanx_right_in[0], bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[11]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_bottom_track_25 (
|
||||
.in({chanx_right_in[12], bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[12]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_right_track_18 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_right_track_20 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_right_track_22 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_bottom_track_19 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_bottom_track_21 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_bottom_track_23 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_bottom_track_25 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for sb_0__1_ -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,526 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for Unique Switch Blocks[1][0]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for sb_1__0_ -----
|
||||
module sb_1__0_(prog_clk,
|
||||
chany_top_in,
|
||||
top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
|
||||
top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
chanx_left_in,
|
||||
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_,
|
||||
left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
ccff_head,
|
||||
chany_top_out,
|
||||
chanx_left_out,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chany_top_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chanx_left_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chany_top_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chanx_left_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_1_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_2_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_3_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_4_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_5_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_6_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
|
||||
wire [0:1] mux_tree_tapbuf_size3_0_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_10_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_10_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_11_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_11_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_1_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_2_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_2_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_3_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_3_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_4_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_4_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_5_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_5_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_6_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_6_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_7_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_7_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_8_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_8_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_9_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_9_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail;
|
||||
wire [0:2] mux_tree_tapbuf_size4_0_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_1_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_2_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_3_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_4_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_4_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_5_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_5_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_6_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_6_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
mux_tree_tapbuf_size4 mux_top_track_0 (
|
||||
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[0]}),
|
||||
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
|
||||
.out(chany_top_out[0]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_top_track_2 (
|
||||
.in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[12]}),
|
||||
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
|
||||
.out(chany_top_out[1]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_top_track_14 (
|
||||
.in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[6]}),
|
||||
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
|
||||
.out(chany_top_out[7]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_left_track_1 (
|
||||
.in({chany_top_in[0], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
|
||||
.out(chanx_left_out[0]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_left_track_3 (
|
||||
.in({chany_top_in[12], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size4_4_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]),
|
||||
.out(chanx_left_out[1]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_left_track_13 (
|
||||
.in({chany_top_in[7], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size4_5_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]),
|
||||
.out(chanx_left_out[6]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_left_track_15 (
|
||||
.in({chany_top_in[6], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size4_6_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]),
|
||||
.out(chanx_left_out[7]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_top_track_0 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(ccff_head),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_top_track_2 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_top_track_14 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_left_track_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_left_track_3 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_left_track_13 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_5_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_left_track_15 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_6_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_top_track_4 (
|
||||
.in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[11]}),
|
||||
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
|
||||
.out(chany_top_out[2]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_top_track_6 (
|
||||
.in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10]}),
|
||||
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
|
||||
.out(chany_top_out[3]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_top_track_8 (
|
||||
.in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[9]}),
|
||||
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]),
|
||||
.out(chany_top_out[4]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_top_track_10 (
|
||||
.in({top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[8]}),
|
||||
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]),
|
||||
.out(chany_top_out[5]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_top_track_12 (
|
||||
.in({top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[7]}),
|
||||
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]),
|
||||
.out(chany_top_out[6]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_top_track_16 (
|
||||
.in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[5]}),
|
||||
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]),
|
||||
.out(chany_top_out[8]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_left_track_5 (
|
||||
.in({chany_top_in[11], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_6_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]),
|
||||
.out(chanx_left_out[2]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_left_track_7 (
|
||||
.in({chany_top_in[10], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_7_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]),
|
||||
.out(chanx_left_out[3]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_left_track_9 (
|
||||
.in({chany_top_in[9], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_8_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]),
|
||||
.out(chanx_left_out[4]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_left_track_11 (
|
||||
.in({chany_top_in[8], left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_9_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]),
|
||||
.out(chanx_left_out[5]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_left_track_17 (
|
||||
.in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_10_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]),
|
||||
.out(chanx_left_out[8]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_left_track_25 (
|
||||
.in({chany_top_in[1], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_11_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]),
|
||||
.out(chanx_left_out[12]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_top_track_4 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_top_track_6 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_top_track_8 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_top_track_10 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_top_track_12 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_top_track_16 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_left_track_5 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_left_track_7 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_7_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_left_track_9 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_8_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_left_track_11 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_9_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_left_track_17 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_10_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_left_track_25 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_11_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_top_track_18 (
|
||||
.in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[4]}),
|
||||
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
|
||||
.out(chany_top_out[9]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_top_track_20 (
|
||||
.in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3]}),
|
||||
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
|
||||
.out(chany_top_out[10]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_top_track_22 (
|
||||
.in({top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[2]}),
|
||||
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
|
||||
.out(chany_top_out[11]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_top_track_24 (
|
||||
.in({top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[1]}),
|
||||
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
|
||||
.out(chany_top_out[12]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_left_track_19 (
|
||||
.in({chany_top_in[4], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
|
||||
.out(chanx_left_out[9]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_left_track_21 (
|
||||
.in({chany_top_in[3], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
|
||||
.out(chanx_left_out[10]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_left_track_23 (
|
||||
.in({chany_top_in[2], left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
|
||||
.out(chanx_left_out[11]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_top_track_18 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_top_track_20 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_top_track_22 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_top_track_24 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_left_track_19 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_left_track_21 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_left_track_23 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for sb_1__0_ -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,526 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for Unique Switch Blocks[1][1]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for sb_1__1_ -----
|
||||
module sb_1__1_(prog_clk,
|
||||
chany_bottom_in,
|
||||
bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
|
||||
chanx_left_in,
|
||||
left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
|
||||
ccff_head,
|
||||
chany_bottom_out,
|
||||
chanx_left_out,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chany_bottom_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:12] chanx_left_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chany_bottom_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:12] chanx_left_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_1_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_2_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_3_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_4_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size2_5_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
|
||||
wire [0:1] mux_tree_tapbuf_size3_0_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_10_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_10_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_11_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_11_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_12_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_12_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_13_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_13_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_14_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_14_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_15_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_15_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_1_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_2_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_2_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_3_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_3_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_4_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_4_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_5_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_5_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_6_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_6_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_7_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_7_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_8_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_8_sram_inv;
|
||||
wire [0:1] mux_tree_tapbuf_size3_9_sram;
|
||||
wire [0:1] mux_tree_tapbuf_size3_9_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_13_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_14_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail;
|
||||
wire [0:2] mux_tree_tapbuf_size4_0_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_1_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_2_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
|
||||
wire [0:2] mux_tree_tapbuf_size4_3_sram;
|
||||
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
mux_tree_tapbuf_size4 mux_bottom_track_1 (
|
||||
.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[1]}),
|
||||
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
|
||||
.out(chany_bottom_out[0]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_bottom_track_13 (
|
||||
.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[7]}),
|
||||
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
|
||||
.out(chany_bottom_out[6]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_left_track_1 (
|
||||
.in({chany_bottom_in[12], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
|
||||
.out(chanx_left_out[0]));
|
||||
|
||||
mux_tree_tapbuf_size4 mux_left_track_13 (
|
||||
.in({chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
|
||||
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
|
||||
.out(chanx_left_out[6]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_bottom_track_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(ccff_head),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_bottom_track_13 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_left_track_1 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size4_mem mem_left_track_13 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
|
||||
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_bottom_track_3 (
|
||||
.in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[2]}),
|
||||
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[1]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_bottom_track_5 (
|
||||
.in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3]}),
|
||||
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[2]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_bottom_track_7 (
|
||||
.in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[4]}),
|
||||
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[3]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_bottom_track_9 (
|
||||
.in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[5]}),
|
||||
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[4]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_bottom_track_11 (
|
||||
.in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[6]}),
|
||||
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[5]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_bottom_track_15 (
|
||||
.in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[8]}),
|
||||
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[7]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_bottom_track_17 (
|
||||
.in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[9]}),
|
||||
.sram(mux_tree_tapbuf_size3_6_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[8]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_bottom_track_25 (
|
||||
.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[0]}),
|
||||
.sram(mux_tree_tapbuf_size3_7_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[12]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_left_track_3 (
|
||||
.in({chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_8_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]),
|
||||
.out(chanx_left_out[1]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_left_track_5 (
|
||||
.in({chany_bottom_in[1], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_9_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]),
|
||||
.out(chanx_left_out[2]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_left_track_7 (
|
||||
.in({chany_bottom_in[2], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_10_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]),
|
||||
.out(chanx_left_out[3]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_left_track_9 (
|
||||
.in({chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_11_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]),
|
||||
.out(chanx_left_out[4]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_left_track_11 (
|
||||
.in({chany_bottom_in[4], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_12_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_12_sram_inv[0:1]),
|
||||
.out(chanx_left_out[5]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_left_track_15 (
|
||||
.in({chany_bottom_in[6], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_13_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_13_sram_inv[0:1]),
|
||||
.out(chanx_left_out[7]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_left_track_17 (
|
||||
.in({chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}),
|
||||
.sram(mux_tree_tapbuf_size3_14_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_14_sram_inv[0:1]),
|
||||
.out(chanx_left_out[8]));
|
||||
|
||||
mux_tree_tapbuf_size3 mux_left_track_25 (
|
||||
.in({chany_bottom_in[11], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size3_15_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size3_15_sram_inv[0:1]),
|
||||
.out(chanx_left_out[12]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_bottom_track_3 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_bottom_track_5 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_bottom_track_7 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_bottom_track_9 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_bottom_track_11 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_bottom_track_15 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_bottom_track_17 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_bottom_track_25 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_7_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_left_track_3 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_8_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_left_track_5 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_9_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_left_track_7 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_10_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_left_track_9 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_11_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_left_track_11 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_12_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_12_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_left_track_15 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_13_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_13_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_left_track_17 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size3_mem_14_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_14_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_14_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size3_mem mem_left_track_25 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size3_15_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size3_15_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_bottom_track_19 (
|
||||
.in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10]}),
|
||||
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[9]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_bottom_track_21 (
|
||||
.in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[11]}),
|
||||
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[10]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_bottom_track_23 (
|
||||
.in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[12]}),
|
||||
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[11]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_left_track_19 (
|
||||
.in({chany_bottom_in[8], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
|
||||
.out(chanx_left_out[9]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_left_track_21 (
|
||||
.in({chany_bottom_in[9], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
|
||||
.out(chanx_left_out[10]));
|
||||
|
||||
mux_tree_tapbuf_size2 mux_left_track_23 (
|
||||
.in({chany_bottom_in[10], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}),
|
||||
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
|
||||
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
|
||||
.out(chanx_left_out[11]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_bottom_track_19 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_bottom_track_21 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_bottom_track_23 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_left_track_19 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size3_mem_14_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_left_track_21 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]));
|
||||
|
||||
mux_tree_tapbuf_size2_mem mem_left_track_23 (
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
|
||||
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
|
||||
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for sb_1__1_ -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Decoders for fabric configuration protocol
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
|
|
@ -0,0 +1,196 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Essential gates
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for const0 -----
|
||||
module const0(const0);
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] const0;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
assign const0[0] = 1'b0;
|
||||
endmodule
|
||||
// ----- END Verilog module for const0 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for const1 -----
|
||||
module const1(const1);
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] const1;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
assign const1[0] = 1'b1;
|
||||
endmodule
|
||||
// ----- END Verilog module for const1 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for INVTX1 -----
|
||||
module INVTX1(in,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] in;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
// ----- Verilog codes of a regular inverter -----
|
||||
assign out = (in === 1'bz)? $random : ~in;
|
||||
|
||||
`ifdef ENABLE_TIMING
|
||||
// ------ BEGIN Pin-to-pin Timing constraints -----
|
||||
specify
|
||||
(in => out) = (0.01, 0.01);
|
||||
endspecify
|
||||
// ------ END Pin-to-pin Timing constraints -----
|
||||
`endif
|
||||
endmodule
|
||||
// ----- END Verilog module for INVTX1 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for buf4 -----
|
||||
module buf4(in,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] in;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
// ----- Verilog codes of a regular inverter -----
|
||||
assign out = (in === 1'bz)? $random : in;
|
||||
|
||||
`ifdef ENABLE_TIMING
|
||||
// ------ BEGIN Pin-to-pin Timing constraints -----
|
||||
specify
|
||||
(in => out) = (0.01, 0.01);
|
||||
endspecify
|
||||
// ------ END Pin-to-pin Timing constraints -----
|
||||
`endif
|
||||
endmodule
|
||||
// ----- END Verilog module for buf4 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for tap_buf4 -----
|
||||
module tap_buf4(in,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] in;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
// ----- Verilog codes of a regular inverter -----
|
||||
assign out = (in === 1'bz)? $random : ~in;
|
||||
|
||||
`ifdef ENABLE_TIMING
|
||||
// ------ BEGIN Pin-to-pin Timing constraints -----
|
||||
specify
|
||||
(in => out) = (0.01, 0.01);
|
||||
endspecify
|
||||
// ------ END Pin-to-pin Timing constraints -----
|
||||
`endif
|
||||
endmodule
|
||||
// ----- END Verilog module for tap_buf4 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for TGATE -----
|
||||
module TGATE(in,
|
||||
sel,
|
||||
selb,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] sel;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] selb;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
assign out = sel ? in : 1'bz;
|
||||
|
||||
`ifdef ENABLE_TIMING
|
||||
// ------ BEGIN Pin-to-pin Timing constraints -----
|
||||
specify
|
||||
(in => out) = (0.01, 0.01);
|
||||
(sel => out) = (0.005, 0.005);
|
||||
(selb => out) = (0.005, 0.005);
|
||||
endspecify
|
||||
// ------ END Pin-to-pin Timing constraints -----
|
||||
`endif
|
||||
endmodule
|
||||
// ----- END Verilog module for TGATE -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Local Decoders for Multiplexers
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Look-Up Tables
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for lut4 -----
|
||||
module lut4(in,
|
||||
sram,
|
||||
sram_inv,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:3] in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:15] sram;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:15] sram_inv;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:3] in;
|
||||
wire [0:0] out;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] INVTX1_0_out;
|
||||
wire [0:0] INVTX1_1_out;
|
||||
wire [0:0] INVTX1_2_out;
|
||||
wire [0:0] INVTX1_3_out;
|
||||
wire [0:0] buf4_0_out;
|
||||
wire [0:0] buf4_1_out;
|
||||
wire [0:0] buf4_2_out;
|
||||
wire [0:0] buf4_3_out;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
INVTX1 INVTX1_0_ (
|
||||
.in(in[0]),
|
||||
.out(INVTX1_0_out));
|
||||
|
||||
INVTX1 INVTX1_1_ (
|
||||
.in(in[1]),
|
||||
.out(INVTX1_1_out));
|
||||
|
||||
INVTX1 INVTX1_2_ (
|
||||
.in(in[2]),
|
||||
.out(INVTX1_2_out));
|
||||
|
||||
INVTX1 INVTX1_3_ (
|
||||
.in(in[3]),
|
||||
.out(INVTX1_3_out));
|
||||
|
||||
buf4 buf4_0_ (
|
||||
.in(in[0]),
|
||||
.out(buf4_0_out));
|
||||
|
||||
buf4 buf4_1_ (
|
||||
.in(in[1]),
|
||||
.out(buf4_1_out));
|
||||
|
||||
buf4 buf4_2_ (
|
||||
.in(in[2]),
|
||||
.out(buf4_2_out));
|
||||
|
||||
buf4 buf4_3_ (
|
||||
.in(in[3]),
|
||||
.out(buf4_3_out));
|
||||
|
||||
lut4_mux lut4_mux_0_ (
|
||||
.in(sram[0:15]),
|
||||
.sram({buf4_0_out, buf4_1_out, buf4_2_out, buf4_3_out}),
|
||||
.sram_inv({INVTX1_0_out, INVTX1_1_out, INVTX1_2_out, INVTX1_3_out}),
|
||||
.out(out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for lut4 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,503 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Memories used in FPGA
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for mux_tree_tapbuf_size6_mem -----
|
||||
module mux_tree_tapbuf_size6_mem(prog_clk,
|
||||
ccff_head,
|
||||
ccff_tail,
|
||||
mem_out,
|
||||
mem_outb);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:2] mem_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:2] mem_outb;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
assign ccff_tail[0] = mem_out[2];
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
DFF DFF_0_ (
|
||||
.CK(prog_clk),
|
||||
.D(ccff_head),
|
||||
.Q(mem_out[0]),
|
||||
.QN(mem_outb[0]));
|
||||
|
||||
DFF DFF_1_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[0]),
|
||||
.Q(mem_out[1]),
|
||||
.QN(mem_outb[1]));
|
||||
|
||||
DFF DFF_2_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[1]),
|
||||
.Q(mem_out[2]),
|
||||
.QN(mem_outb[2]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for mux_tree_tapbuf_size6_mem -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for mux_tree_tapbuf_size4_mem -----
|
||||
module mux_tree_tapbuf_size4_mem(prog_clk,
|
||||
ccff_head,
|
||||
ccff_tail,
|
||||
mem_out,
|
||||
mem_outb);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:2] mem_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:2] mem_outb;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
assign ccff_tail[0] = mem_out[2];
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
DFF DFF_0_ (
|
||||
.CK(prog_clk),
|
||||
.D(ccff_head),
|
||||
.Q(mem_out[0]),
|
||||
.QN(mem_outb[0]));
|
||||
|
||||
DFF DFF_1_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[0]),
|
||||
.Q(mem_out[1]),
|
||||
.QN(mem_outb[1]));
|
||||
|
||||
DFF DFF_2_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[1]),
|
||||
.Q(mem_out[2]),
|
||||
.QN(mem_outb[2]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for mux_tree_tapbuf_size4_mem -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for mux_tree_tapbuf_size3_mem -----
|
||||
module mux_tree_tapbuf_size3_mem(prog_clk,
|
||||
ccff_head,
|
||||
ccff_tail,
|
||||
mem_out,
|
||||
mem_outb);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:1] mem_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:1] mem_outb;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
assign ccff_tail[0] = mem_out[1];
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
DFF DFF_0_ (
|
||||
.CK(prog_clk),
|
||||
.D(ccff_head),
|
||||
.Q(mem_out[0]),
|
||||
.QN(mem_outb[0]));
|
||||
|
||||
DFF DFF_1_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[0]),
|
||||
.Q(mem_out[1]),
|
||||
.QN(mem_outb[1]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for mux_tree_tapbuf_size3_mem -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for mux_tree_tapbuf_size2_mem -----
|
||||
module mux_tree_tapbuf_size2_mem(prog_clk,
|
||||
ccff_head,
|
||||
ccff_tail,
|
||||
mem_out,
|
||||
mem_outb);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:1] mem_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:1] mem_outb;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
assign ccff_tail[0] = mem_out[1];
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
DFF DFF_0_ (
|
||||
.CK(prog_clk),
|
||||
.D(ccff_head),
|
||||
.Q(mem_out[0]),
|
||||
.QN(mem_outb[0]));
|
||||
|
||||
DFF DFF_1_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[0]),
|
||||
.Q(mem_out[1]),
|
||||
.QN(mem_outb[1]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for mux_tree_tapbuf_size2_mem -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for mux_tree_size14_mem -----
|
||||
module mux_tree_size14_mem(prog_clk,
|
||||
ccff_head,
|
||||
ccff_tail,
|
||||
mem_out,
|
||||
mem_outb);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:3] mem_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:3] mem_outb;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
assign ccff_tail[0] = mem_out[3];
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
DFF DFF_0_ (
|
||||
.CK(prog_clk),
|
||||
.D(ccff_head),
|
||||
.Q(mem_out[0]),
|
||||
.QN(mem_outb[0]));
|
||||
|
||||
DFF DFF_1_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[0]),
|
||||
.Q(mem_out[1]),
|
||||
.QN(mem_outb[1]));
|
||||
|
||||
DFF DFF_2_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[1]),
|
||||
.Q(mem_out[2]),
|
||||
.QN(mem_outb[2]));
|
||||
|
||||
DFF DFF_3_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[2]),
|
||||
.Q(mem_out[3]),
|
||||
.QN(mem_outb[3]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for mux_tree_size14_mem -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for lut4_DFF_mem -----
|
||||
module lut4_DFF_mem(prog_clk,
|
||||
ccff_head,
|
||||
ccff_tail,
|
||||
mem_out,
|
||||
mem_outb);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:15] mem_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:15] mem_outb;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
assign ccff_tail[0] = mem_out[15];
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
DFF DFF_0_ (
|
||||
.CK(prog_clk),
|
||||
.D(ccff_head),
|
||||
.Q(mem_out[0]),
|
||||
.QN(mem_outb[0]));
|
||||
|
||||
DFF DFF_1_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[0]),
|
||||
.Q(mem_out[1]),
|
||||
.QN(mem_outb[1]));
|
||||
|
||||
DFF DFF_2_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[1]),
|
||||
.Q(mem_out[2]),
|
||||
.QN(mem_outb[2]));
|
||||
|
||||
DFF DFF_3_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[2]),
|
||||
.Q(mem_out[3]),
|
||||
.QN(mem_outb[3]));
|
||||
|
||||
DFF DFF_4_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[3]),
|
||||
.Q(mem_out[4]),
|
||||
.QN(mem_outb[4]));
|
||||
|
||||
DFF DFF_5_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[4]),
|
||||
.Q(mem_out[5]),
|
||||
.QN(mem_outb[5]));
|
||||
|
||||
DFF DFF_6_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[5]),
|
||||
.Q(mem_out[6]),
|
||||
.QN(mem_outb[6]));
|
||||
|
||||
DFF DFF_7_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[6]),
|
||||
.Q(mem_out[7]),
|
||||
.QN(mem_outb[7]));
|
||||
|
||||
DFF DFF_8_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[7]),
|
||||
.Q(mem_out[8]),
|
||||
.QN(mem_outb[8]));
|
||||
|
||||
DFF DFF_9_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[8]),
|
||||
.Q(mem_out[9]),
|
||||
.QN(mem_outb[9]));
|
||||
|
||||
DFF DFF_10_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[9]),
|
||||
.Q(mem_out[10]),
|
||||
.QN(mem_outb[10]));
|
||||
|
||||
DFF DFF_11_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[10]),
|
||||
.Q(mem_out[11]),
|
||||
.QN(mem_outb[11]));
|
||||
|
||||
DFF DFF_12_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[11]),
|
||||
.Q(mem_out[12]),
|
||||
.QN(mem_outb[12]));
|
||||
|
||||
DFF DFF_13_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[12]),
|
||||
.Q(mem_out[13]),
|
||||
.QN(mem_outb[13]));
|
||||
|
||||
DFF DFF_14_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[13]),
|
||||
.Q(mem_out[14]),
|
||||
.QN(mem_outb[14]));
|
||||
|
||||
DFF DFF_15_ (
|
||||
.CK(prog_clk),
|
||||
.D(mem_out[14]),
|
||||
.Q(mem_out[15]),
|
||||
.QN(mem_outb[15]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for lut4_DFF_mem -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for GPIO_DFF_mem -----
|
||||
module GPIO_DFF_mem(prog_clk,
|
||||
ccff_head,
|
||||
ccff_tail,
|
||||
mem_out,
|
||||
mem_outb);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] mem_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] mem_outb;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
assign ccff_tail[0] = mem_out[0];
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
DFF DFF_0_ (
|
||||
.CK(prog_clk),
|
||||
.D(ccff_head),
|
||||
.Q(mem_out),
|
||||
.QN(mem_outb));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for GPIO_DFF_mem -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Multiplexer primitives
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for mux_tree_tapbuf_basis_input2_mem1 -----
|
||||
module mux_tree_tapbuf_basis_input2_mem1(in,
|
||||
mem,
|
||||
mem_inv,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:1] in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] mem;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] mem_inv;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
TGATE TGATE_0_ (
|
||||
.in(in[0]),
|
||||
.sel(mem),
|
||||
.selb(mem_inv),
|
||||
.out(out));
|
||||
|
||||
TGATE TGATE_1_ (
|
||||
.in(in[1]),
|
||||
.sel(mem_inv),
|
||||
.selb(mem),
|
||||
.out(out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for mux_tree_tapbuf_basis_input2_mem1 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for mux_tree_basis_input2_mem1 -----
|
||||
module mux_tree_basis_input2_mem1(in,
|
||||
mem,
|
||||
mem_inv,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:1] in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] mem;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] mem_inv;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
TGATE TGATE_0_ (
|
||||
.in(in[0]),
|
||||
.sel(mem),
|
||||
.selb(mem_inv),
|
||||
.out(out));
|
||||
|
||||
TGATE TGATE_1_ (
|
||||
.in(in[1]),
|
||||
.sel(mem_inv),
|
||||
.selb(mem),
|
||||
.out(out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for mux_tree_basis_input2_mem1 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for lut4_mux_basis_input2_mem1 -----
|
||||
module lut4_mux_basis_input2_mem1(in,
|
||||
mem,
|
||||
mem_inv,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:1] in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] mem;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] mem_inv;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
TGATE TGATE_0_ (
|
||||
.in(in[0]),
|
||||
.sel(mem),
|
||||
.selb(mem_inv),
|
||||
.out(out));
|
||||
|
||||
TGATE TGATE_1_ (
|
||||
.in(in[1]),
|
||||
.sel(mem_inv),
|
||||
.selb(mem),
|
||||
.out(out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for lut4_mux_basis_input2_mem1 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,826 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Multiplexers
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for mux_tree_tapbuf_size6 -----
|
||||
module mux_tree_tapbuf_size6(in,
|
||||
sram,
|
||||
sram_inv,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:5] in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:2] sram;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:2] sram_inv;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] INVTX1_0_out;
|
||||
wire [0:0] INVTX1_1_out;
|
||||
wire [0:0] INVTX1_2_out;
|
||||
wire [0:0] INVTX1_3_out;
|
||||
wire [0:0] INVTX1_4_out;
|
||||
wire [0:0] INVTX1_5_out;
|
||||
wire [0:0] const1_0_const1;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_2_out;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_3_out;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_4_out;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_5_out;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
INVTX1 INVTX1_0_ (
|
||||
.in(in[0]),
|
||||
.out(INVTX1_0_out));
|
||||
|
||||
INVTX1 INVTX1_1_ (
|
||||
.in(in[1]),
|
||||
.out(INVTX1_1_out));
|
||||
|
||||
INVTX1 INVTX1_2_ (
|
||||
.in(in[2]),
|
||||
.out(INVTX1_2_out));
|
||||
|
||||
INVTX1 INVTX1_3_ (
|
||||
.in(in[3]),
|
||||
.out(INVTX1_3_out));
|
||||
|
||||
INVTX1 INVTX1_4_ (
|
||||
.in(in[4]),
|
||||
.out(INVTX1_4_out));
|
||||
|
||||
INVTX1 INVTX1_5_ (
|
||||
.in(in[5]),
|
||||
.out(INVTX1_5_out));
|
||||
|
||||
const1 const1_0_ (
|
||||
.const1(const1_0_const1));
|
||||
|
||||
tap_buf4 tap_buf4_0_ (
|
||||
.in(mux_tree_tapbuf_basis_input2_mem1_5_out),
|
||||
.out(out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ (
|
||||
.in({INVTX1_0_out, INVTX1_1_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_0_out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_1_ (
|
||||
.in({INVTX1_2_out, INVTX1_3_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_1_out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_2_ (
|
||||
.in({INVTX1_4_out, INVTX1_5_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_2_out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
|
||||
.in({mux_tree_tapbuf_basis_input2_mem1_0_out, mux_tree_tapbuf_basis_input2_mem1_1_out}),
|
||||
.mem(sram[1]),
|
||||
.mem_inv(sram_inv[1]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_3_out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_1_ (
|
||||
.in({mux_tree_tapbuf_basis_input2_mem1_2_out, const1_0_const1}),
|
||||
.mem(sram[1]),
|
||||
.mem_inv(sram_inv[1]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_4_out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l3_in_0_ (
|
||||
.in({mux_tree_tapbuf_basis_input2_mem1_3_out, mux_tree_tapbuf_basis_input2_mem1_4_out}),
|
||||
.mem(sram[2]),
|
||||
.mem_inv(sram_inv[2]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_5_out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for mux_tree_tapbuf_size6 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for mux_tree_tapbuf_size4 -----
|
||||
module mux_tree_tapbuf_size4(in,
|
||||
sram,
|
||||
sram_inv,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:3] in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:2] sram;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:2] sram_inv;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] INVTX1_0_out;
|
||||
wire [0:0] INVTX1_1_out;
|
||||
wire [0:0] INVTX1_2_out;
|
||||
wire [0:0] INVTX1_3_out;
|
||||
wire [0:0] const1_0_const1;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_2_out;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_3_out;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
INVTX1 INVTX1_0_ (
|
||||
.in(in[0]),
|
||||
.out(INVTX1_0_out));
|
||||
|
||||
INVTX1 INVTX1_1_ (
|
||||
.in(in[1]),
|
||||
.out(INVTX1_1_out));
|
||||
|
||||
INVTX1 INVTX1_2_ (
|
||||
.in(in[2]),
|
||||
.out(INVTX1_2_out));
|
||||
|
||||
INVTX1 INVTX1_3_ (
|
||||
.in(in[3]),
|
||||
.out(INVTX1_3_out));
|
||||
|
||||
const1 const1_0_ (
|
||||
.const1(const1_0_const1));
|
||||
|
||||
tap_buf4 tap_buf4_0_ (
|
||||
.in(mux_tree_tapbuf_basis_input2_mem1_3_out),
|
||||
.out(out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ (
|
||||
.in({INVTX1_0_out, INVTX1_1_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_0_out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
|
||||
.in({mux_tree_tapbuf_basis_input2_mem1_0_out, INVTX1_2_out}),
|
||||
.mem(sram[1]),
|
||||
.mem_inv(sram_inv[1]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_1_out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_1_ (
|
||||
.in({INVTX1_3_out, const1_0_const1}),
|
||||
.mem(sram[1]),
|
||||
.mem_inv(sram_inv[1]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_2_out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l3_in_0_ (
|
||||
.in({mux_tree_tapbuf_basis_input2_mem1_1_out, mux_tree_tapbuf_basis_input2_mem1_2_out}),
|
||||
.mem(sram[2]),
|
||||
.mem_inv(sram_inv[2]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_3_out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for mux_tree_tapbuf_size4 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for mux_tree_tapbuf_size3 -----
|
||||
module mux_tree_tapbuf_size3(in,
|
||||
sram,
|
||||
sram_inv,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:2] in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:1] sram;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:1] sram_inv;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] INVTX1_0_out;
|
||||
wire [0:0] INVTX1_1_out;
|
||||
wire [0:0] INVTX1_2_out;
|
||||
wire [0:0] const1_0_const1;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_2_out;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
INVTX1 INVTX1_0_ (
|
||||
.in(in[0]),
|
||||
.out(INVTX1_0_out));
|
||||
|
||||
INVTX1 INVTX1_1_ (
|
||||
.in(in[1]),
|
||||
.out(INVTX1_1_out));
|
||||
|
||||
INVTX1 INVTX1_2_ (
|
||||
.in(in[2]),
|
||||
.out(INVTX1_2_out));
|
||||
|
||||
const1 const1_0_ (
|
||||
.const1(const1_0_const1));
|
||||
|
||||
tap_buf4 tap_buf4_0_ (
|
||||
.in(mux_tree_tapbuf_basis_input2_mem1_2_out),
|
||||
.out(out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ (
|
||||
.in({INVTX1_0_out, INVTX1_1_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_0_out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_1_ (
|
||||
.in({INVTX1_2_out, const1_0_const1}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_1_out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
|
||||
.in({mux_tree_tapbuf_basis_input2_mem1_0_out, mux_tree_tapbuf_basis_input2_mem1_1_out}),
|
||||
.mem(sram[1]),
|
||||
.mem_inv(sram_inv[1]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_2_out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for mux_tree_tapbuf_size3 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for mux_tree_tapbuf_size2 -----
|
||||
module mux_tree_tapbuf_size2(in,
|
||||
sram,
|
||||
sram_inv,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:1] in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:1] sram;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:1] sram_inv;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] INVTX1_0_out;
|
||||
wire [0:0] INVTX1_1_out;
|
||||
wire [0:0] const1_0_const1;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out;
|
||||
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
INVTX1 INVTX1_0_ (
|
||||
.in(in[0]),
|
||||
.out(INVTX1_0_out));
|
||||
|
||||
INVTX1 INVTX1_1_ (
|
||||
.in(in[1]),
|
||||
.out(INVTX1_1_out));
|
||||
|
||||
const1 const1_0_ (
|
||||
.const1(const1_0_const1));
|
||||
|
||||
tap_buf4 tap_buf4_0_ (
|
||||
.in(mux_tree_tapbuf_basis_input2_mem1_1_out),
|
||||
.out(out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ (
|
||||
.in({INVTX1_0_out, INVTX1_1_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_0_out));
|
||||
|
||||
mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
|
||||
.in({mux_tree_tapbuf_basis_input2_mem1_0_out, const1_0_const1}),
|
||||
.mem(sram[1]),
|
||||
.mem_inv(sram_inv[1]),
|
||||
.out(mux_tree_tapbuf_basis_input2_mem1_1_out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for mux_tree_tapbuf_size2 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for mux_tree_size14 -----
|
||||
module mux_tree_size14(in,
|
||||
sram,
|
||||
sram_inv,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:13] in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:3] sram;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:3] sram_inv;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] INVTX1_0_out;
|
||||
wire [0:0] INVTX1_10_out;
|
||||
wire [0:0] INVTX1_11_out;
|
||||
wire [0:0] INVTX1_12_out;
|
||||
wire [0:0] INVTX1_13_out;
|
||||
wire [0:0] INVTX1_1_out;
|
||||
wire [0:0] INVTX1_2_out;
|
||||
wire [0:0] INVTX1_3_out;
|
||||
wire [0:0] INVTX1_4_out;
|
||||
wire [0:0] INVTX1_5_out;
|
||||
wire [0:0] INVTX1_6_out;
|
||||
wire [0:0] INVTX1_7_out;
|
||||
wire [0:0] INVTX1_8_out;
|
||||
wire [0:0] INVTX1_9_out;
|
||||
wire [0:0] const1_0_const1;
|
||||
wire [0:0] mux_tree_basis_input2_mem1_0_out;
|
||||
wire [0:0] mux_tree_basis_input2_mem1_10_out;
|
||||
wire [0:0] mux_tree_basis_input2_mem1_11_out;
|
||||
wire [0:0] mux_tree_basis_input2_mem1_12_out;
|
||||
wire [0:0] mux_tree_basis_input2_mem1_13_out;
|
||||
wire [0:0] mux_tree_basis_input2_mem1_1_out;
|
||||
wire [0:0] mux_tree_basis_input2_mem1_2_out;
|
||||
wire [0:0] mux_tree_basis_input2_mem1_3_out;
|
||||
wire [0:0] mux_tree_basis_input2_mem1_4_out;
|
||||
wire [0:0] mux_tree_basis_input2_mem1_5_out;
|
||||
wire [0:0] mux_tree_basis_input2_mem1_6_out;
|
||||
wire [0:0] mux_tree_basis_input2_mem1_7_out;
|
||||
wire [0:0] mux_tree_basis_input2_mem1_8_out;
|
||||
wire [0:0] mux_tree_basis_input2_mem1_9_out;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
INVTX1 INVTX1_0_ (
|
||||
.in(in[0]),
|
||||
.out(INVTX1_0_out));
|
||||
|
||||
INVTX1 INVTX1_1_ (
|
||||
.in(in[1]),
|
||||
.out(INVTX1_1_out));
|
||||
|
||||
INVTX1 INVTX1_2_ (
|
||||
.in(in[2]),
|
||||
.out(INVTX1_2_out));
|
||||
|
||||
INVTX1 INVTX1_3_ (
|
||||
.in(in[3]),
|
||||
.out(INVTX1_3_out));
|
||||
|
||||
INVTX1 INVTX1_4_ (
|
||||
.in(in[4]),
|
||||
.out(INVTX1_4_out));
|
||||
|
||||
INVTX1 INVTX1_5_ (
|
||||
.in(in[5]),
|
||||
.out(INVTX1_5_out));
|
||||
|
||||
INVTX1 INVTX1_6_ (
|
||||
.in(in[6]),
|
||||
.out(INVTX1_6_out));
|
||||
|
||||
INVTX1 INVTX1_7_ (
|
||||
.in(in[7]),
|
||||
.out(INVTX1_7_out));
|
||||
|
||||
INVTX1 INVTX1_8_ (
|
||||
.in(in[8]),
|
||||
.out(INVTX1_8_out));
|
||||
|
||||
INVTX1 INVTX1_9_ (
|
||||
.in(in[9]),
|
||||
.out(INVTX1_9_out));
|
||||
|
||||
INVTX1 INVTX1_10_ (
|
||||
.in(in[10]),
|
||||
.out(INVTX1_10_out));
|
||||
|
||||
INVTX1 INVTX1_11_ (
|
||||
.in(in[11]),
|
||||
.out(INVTX1_11_out));
|
||||
|
||||
INVTX1 INVTX1_12_ (
|
||||
.in(in[12]),
|
||||
.out(INVTX1_12_out));
|
||||
|
||||
INVTX1 INVTX1_13_ (
|
||||
.in(in[13]),
|
||||
.out(INVTX1_13_out));
|
||||
|
||||
INVTX1 INVTX1_14_ (
|
||||
.in(mux_tree_basis_input2_mem1_13_out),
|
||||
.out(out));
|
||||
|
||||
const1 const1_0_ (
|
||||
.const1(const1_0_const1));
|
||||
|
||||
mux_tree_basis_input2_mem1 mux_l1_in_0_ (
|
||||
.in({INVTX1_0_out, INVTX1_1_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(mux_tree_basis_input2_mem1_0_out));
|
||||
|
||||
mux_tree_basis_input2_mem1 mux_l1_in_1_ (
|
||||
.in({INVTX1_2_out, INVTX1_3_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(mux_tree_basis_input2_mem1_1_out));
|
||||
|
||||
mux_tree_basis_input2_mem1 mux_l1_in_2_ (
|
||||
.in({INVTX1_4_out, INVTX1_5_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(mux_tree_basis_input2_mem1_2_out));
|
||||
|
||||
mux_tree_basis_input2_mem1 mux_l1_in_3_ (
|
||||
.in({INVTX1_6_out, INVTX1_7_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(mux_tree_basis_input2_mem1_3_out));
|
||||
|
||||
mux_tree_basis_input2_mem1 mux_l1_in_4_ (
|
||||
.in({INVTX1_8_out, INVTX1_9_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(mux_tree_basis_input2_mem1_4_out));
|
||||
|
||||
mux_tree_basis_input2_mem1 mux_l1_in_5_ (
|
||||
.in({INVTX1_10_out, INVTX1_11_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(mux_tree_basis_input2_mem1_5_out));
|
||||
|
||||
mux_tree_basis_input2_mem1 mux_l1_in_6_ (
|
||||
.in({INVTX1_12_out, INVTX1_13_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(mux_tree_basis_input2_mem1_6_out));
|
||||
|
||||
mux_tree_basis_input2_mem1 mux_l2_in_0_ (
|
||||
.in({mux_tree_basis_input2_mem1_0_out, mux_tree_basis_input2_mem1_1_out}),
|
||||
.mem(sram[1]),
|
||||
.mem_inv(sram_inv[1]),
|
||||
.out(mux_tree_basis_input2_mem1_7_out));
|
||||
|
||||
mux_tree_basis_input2_mem1 mux_l2_in_1_ (
|
||||
.in({mux_tree_basis_input2_mem1_2_out, mux_tree_basis_input2_mem1_3_out}),
|
||||
.mem(sram[1]),
|
||||
.mem_inv(sram_inv[1]),
|
||||
.out(mux_tree_basis_input2_mem1_8_out));
|
||||
|
||||
mux_tree_basis_input2_mem1 mux_l2_in_2_ (
|
||||
.in({mux_tree_basis_input2_mem1_4_out, mux_tree_basis_input2_mem1_5_out}),
|
||||
.mem(sram[1]),
|
||||
.mem_inv(sram_inv[1]),
|
||||
.out(mux_tree_basis_input2_mem1_9_out));
|
||||
|
||||
mux_tree_basis_input2_mem1 mux_l2_in_3_ (
|
||||
.in({mux_tree_basis_input2_mem1_6_out, const1_0_const1}),
|
||||
.mem(sram[1]),
|
||||
.mem_inv(sram_inv[1]),
|
||||
.out(mux_tree_basis_input2_mem1_10_out));
|
||||
|
||||
mux_tree_basis_input2_mem1 mux_l3_in_0_ (
|
||||
.in({mux_tree_basis_input2_mem1_7_out, mux_tree_basis_input2_mem1_8_out}),
|
||||
.mem(sram[2]),
|
||||
.mem_inv(sram_inv[2]),
|
||||
.out(mux_tree_basis_input2_mem1_11_out));
|
||||
|
||||
mux_tree_basis_input2_mem1 mux_l3_in_1_ (
|
||||
.in({mux_tree_basis_input2_mem1_9_out, mux_tree_basis_input2_mem1_10_out}),
|
||||
.mem(sram[2]),
|
||||
.mem_inv(sram_inv[2]),
|
||||
.out(mux_tree_basis_input2_mem1_12_out));
|
||||
|
||||
mux_tree_basis_input2_mem1 mux_l4_in_0_ (
|
||||
.in({mux_tree_basis_input2_mem1_11_out, mux_tree_basis_input2_mem1_12_out}),
|
||||
.mem(sram[3]),
|
||||
.mem_inv(sram_inv[3]),
|
||||
.out(mux_tree_basis_input2_mem1_13_out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for mux_tree_size14 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for lut4_mux -----
|
||||
module lut4_mux(in,
|
||||
sram,
|
||||
sram_inv,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:15] in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:3] sram;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:3] sram_inv;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] INVTX1_0_out;
|
||||
wire [0:0] INVTX1_10_out;
|
||||
wire [0:0] INVTX1_11_out;
|
||||
wire [0:0] INVTX1_12_out;
|
||||
wire [0:0] INVTX1_13_out;
|
||||
wire [0:0] INVTX1_14_out;
|
||||
wire [0:0] INVTX1_15_out;
|
||||
wire [0:0] INVTX1_1_out;
|
||||
wire [0:0] INVTX1_2_out;
|
||||
wire [0:0] INVTX1_3_out;
|
||||
wire [0:0] INVTX1_4_out;
|
||||
wire [0:0] INVTX1_5_out;
|
||||
wire [0:0] INVTX1_6_out;
|
||||
wire [0:0] INVTX1_7_out;
|
||||
wire [0:0] INVTX1_8_out;
|
||||
wire [0:0] INVTX1_9_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_0_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_10_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_11_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_12_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_13_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_14_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_1_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_2_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_3_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_4_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_5_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_6_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_7_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_8_out;
|
||||
wire [0:0] lut4_mux_basis_input2_mem1_9_out;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
INVTX1 INVTX1_0_ (
|
||||
.in(in[0]),
|
||||
.out(INVTX1_0_out));
|
||||
|
||||
INVTX1 INVTX1_1_ (
|
||||
.in(in[1]),
|
||||
.out(INVTX1_1_out));
|
||||
|
||||
INVTX1 INVTX1_2_ (
|
||||
.in(in[2]),
|
||||
.out(INVTX1_2_out));
|
||||
|
||||
INVTX1 INVTX1_3_ (
|
||||
.in(in[3]),
|
||||
.out(INVTX1_3_out));
|
||||
|
||||
INVTX1 INVTX1_4_ (
|
||||
.in(in[4]),
|
||||
.out(INVTX1_4_out));
|
||||
|
||||
INVTX1 INVTX1_5_ (
|
||||
.in(in[5]),
|
||||
.out(INVTX1_5_out));
|
||||
|
||||
INVTX1 INVTX1_6_ (
|
||||
.in(in[6]),
|
||||
.out(INVTX1_6_out));
|
||||
|
||||
INVTX1 INVTX1_7_ (
|
||||
.in(in[7]),
|
||||
.out(INVTX1_7_out));
|
||||
|
||||
INVTX1 INVTX1_8_ (
|
||||
.in(in[8]),
|
||||
.out(INVTX1_8_out));
|
||||
|
||||
INVTX1 INVTX1_9_ (
|
||||
.in(in[9]),
|
||||
.out(INVTX1_9_out));
|
||||
|
||||
INVTX1 INVTX1_10_ (
|
||||
.in(in[10]),
|
||||
.out(INVTX1_10_out));
|
||||
|
||||
INVTX1 INVTX1_11_ (
|
||||
.in(in[11]),
|
||||
.out(INVTX1_11_out));
|
||||
|
||||
INVTX1 INVTX1_12_ (
|
||||
.in(in[12]),
|
||||
.out(INVTX1_12_out));
|
||||
|
||||
INVTX1 INVTX1_13_ (
|
||||
.in(in[13]),
|
||||
.out(INVTX1_13_out));
|
||||
|
||||
INVTX1 INVTX1_14_ (
|
||||
.in(in[14]),
|
||||
.out(INVTX1_14_out));
|
||||
|
||||
INVTX1 INVTX1_15_ (
|
||||
.in(in[15]),
|
||||
.out(INVTX1_15_out));
|
||||
|
||||
INVTX1 INVTX1_16_ (
|
||||
.in(lut4_mux_basis_input2_mem1_14_out),
|
||||
.out(out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l1_in_0_ (
|
||||
.in({INVTX1_0_out, INVTX1_1_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(lut4_mux_basis_input2_mem1_0_out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l1_in_1_ (
|
||||
.in({INVTX1_2_out, INVTX1_3_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(lut4_mux_basis_input2_mem1_1_out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l1_in_2_ (
|
||||
.in({INVTX1_4_out, INVTX1_5_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(lut4_mux_basis_input2_mem1_2_out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l1_in_3_ (
|
||||
.in({INVTX1_6_out, INVTX1_7_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(lut4_mux_basis_input2_mem1_3_out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l1_in_4_ (
|
||||
.in({INVTX1_8_out, INVTX1_9_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(lut4_mux_basis_input2_mem1_4_out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l1_in_5_ (
|
||||
.in({INVTX1_10_out, INVTX1_11_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(lut4_mux_basis_input2_mem1_5_out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l1_in_6_ (
|
||||
.in({INVTX1_12_out, INVTX1_13_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(lut4_mux_basis_input2_mem1_6_out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l1_in_7_ (
|
||||
.in({INVTX1_14_out, INVTX1_15_out}),
|
||||
.mem(sram[0]),
|
||||
.mem_inv(sram_inv[0]),
|
||||
.out(lut4_mux_basis_input2_mem1_7_out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l2_in_0_ (
|
||||
.in({lut4_mux_basis_input2_mem1_0_out, lut4_mux_basis_input2_mem1_1_out}),
|
||||
.mem(sram[1]),
|
||||
.mem_inv(sram_inv[1]),
|
||||
.out(lut4_mux_basis_input2_mem1_8_out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l2_in_1_ (
|
||||
.in({lut4_mux_basis_input2_mem1_2_out, lut4_mux_basis_input2_mem1_3_out}),
|
||||
.mem(sram[1]),
|
||||
.mem_inv(sram_inv[1]),
|
||||
.out(lut4_mux_basis_input2_mem1_9_out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l2_in_2_ (
|
||||
.in({lut4_mux_basis_input2_mem1_4_out, lut4_mux_basis_input2_mem1_5_out}),
|
||||
.mem(sram[1]),
|
||||
.mem_inv(sram_inv[1]),
|
||||
.out(lut4_mux_basis_input2_mem1_10_out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l2_in_3_ (
|
||||
.in({lut4_mux_basis_input2_mem1_6_out, lut4_mux_basis_input2_mem1_7_out}),
|
||||
.mem(sram[1]),
|
||||
.mem_inv(sram_inv[1]),
|
||||
.out(lut4_mux_basis_input2_mem1_11_out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l3_in_0_ (
|
||||
.in({lut4_mux_basis_input2_mem1_8_out, lut4_mux_basis_input2_mem1_9_out}),
|
||||
.mem(sram[2]),
|
||||
.mem_inv(sram_inv[2]),
|
||||
.out(lut4_mux_basis_input2_mem1_12_out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l3_in_1_ (
|
||||
.in({lut4_mux_basis_input2_mem1_10_out, lut4_mux_basis_input2_mem1_11_out}),
|
||||
.mem(sram[2]),
|
||||
.mem_inv(sram_inv[2]),
|
||||
.out(lut4_mux_basis_input2_mem1_13_out));
|
||||
|
||||
lut4_mux_basis_input2_mem1 mux_l4_in_0_ (
|
||||
.in({lut4_mux_basis_input2_mem1_12_out, lut4_mux_basis_input2_mem1_13_out}),
|
||||
.mem(sram[3]),
|
||||
.mem_inv(sram_inv[3]),
|
||||
.out(lut4_mux_basis_input2_mem1_14_out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for lut4_mux -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Shift register banks used in FPGA
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Template for user-defined Verilog modules
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- Template Verilog module for DFFSRQ -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for DFFSRQ -----
|
||||
module DFFSRQ(SET,
|
||||
RST,
|
||||
CK,
|
||||
D,
|
||||
Q);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] SET;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] RST;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] CK;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] D;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] Q;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
// ----- Internal logic should start here -----
|
||||
|
||||
|
||||
// ----- Internal logic should end here -----
|
||||
endmodule
|
||||
// ----- END Verilog module for DFFSRQ -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
// ----- Template Verilog module for DFF -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for DFF -----
|
||||
module DFF(CK,
|
||||
D,
|
||||
Q,
|
||||
QN);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] CK;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] D;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] Q;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] QN;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
// ----- Internal logic should start here -----
|
||||
|
||||
|
||||
// ----- Internal logic should end here -----
|
||||
endmodule
|
||||
// ----- END Verilog module for DFF -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
// ----- Template Verilog module for GPIO -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for GPIO -----
|
||||
module GPIO(PAD,
|
||||
A,
|
||||
DIR,
|
||||
Y);
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:0] PAD;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] A;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] DIR;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] Y;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
// ----- Internal logic should start here -----
|
||||
|
||||
|
||||
// ----- Internal logic should end here -----
|
||||
endmodule
|
||||
// ----- END Verilog module for GPIO -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Wires
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Verilog modules for regular wires -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for direct_interc -----
|
||||
module direct_interc(in,
|
||||
out);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] in;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] out;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
wire [0:0] in;
|
||||
wire [0:0] out;
|
||||
assign out[0] = in[0];
|
||||
endmodule
|
||||
// ----- END Verilog module for direct_interc -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
// ----- END Verilog modules for regular wires -----
|
||||
Loading…
Reference in New Issue