[test] relax minW for counter128, as VPR's router degrades in routability
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@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
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# VPR parameters
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# # Use a fixed routing channel width to save runtime
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vpr_route_chan_width=60
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vpr_route_chan_width=80
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openfpga_vpr_pack_stats_file=vpr_pack_block_usage.txt
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[ARCHITECTURES]
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