remove minor comments
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@ -78,7 +78,6 @@ bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
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bench17_top = jpeg_qnr
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bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
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bench18_top = multi_enc_decx2x4
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# sdc_controller requires 4 clocks
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#bench19_top = sdc_controller
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#bench19_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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