[HDL] Add a multi-mode ff which can support posedge and negedge

openfpga_flow/openfpga_cell_library/verilog/dff.v

@@ -294,6 +294,33 @@ DFFRQ FF_CORE (.RST(post_rst),
 
 endmodule //End Of Module
 
+//-----------------------------------------------------
+// Function : A multi-functional D-type flip-flop with 
+//           - asynchronous reset 
+//             which can be switched between active-low and active high
+//           - clock
+//             which can be switched between positive edge triggered and negative edge triggered
+//-----------------------------------------------------
+module MULTI_MODE_DFFRCKQ (
+  input RST, // Reset input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
+);
+
+wire post_rst = mode[0] ? ~RST : RST;
+wire post_clk = mode[1] ? ~CK : CK;
+
+DFFRQ FF_CORE (.RST(post_rst),
+               .CK(post_clk),
+               .D(D),
+               .Q(Q)
+               );
+
+endmodule //End Of Module
+
+
 //-----------------------------------------------------
 // Function    : D-type flip-flop with 
 //               - asynchronous active high reset