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[test] fixed a few bugs

This commit is contained in:
tangxifan 2022-07-28 12:06:16 -07:00
parent ca9122ddb9
commit 35fe858035
4 changed files with 33 additions and 151 deletions
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18
openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml Normal file
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@ -0,0 +1,18 @@
<io_coordinates>
<io pad="gfpga_pad_IO_A2F[0]" x="1" y="0" z="0"/>
<io pad="gfpga_pad_IO_F2A[0]" x="1" y="0" z="1"/>
<io pad="gfpga_pad_IO_A2F[1]" x="1" y="0" z="2"/>
<io pad="gfpga_pad_IO_F2A[1]" x="1" y="0" z="3"/>
<io pad="gfpga_pad_IO_A2F[2]" x="1" y="0" z="4"/>
<io pad="gfpga_pad_IO_F2A[2]" x="1" y="0" z="5"/>
<io pad="gfpga_pad_IO_A2F[3]" x="1" y="0" z="6"/>
<io pad="gfpga_pad_IO_F2A[3]" x="1" y="0" z="7"/>
<io pad="gfpga_pad_IO_A2F[4]" x="2" y="0" z="0"/>
<io pad="gfpga_pad_IO_F2A[4]" x="2" y="0" z="1"/>
<io pad="gfpga_pad_IO_A2F[5]" x="2" y="0" z="2"/>
<io pad="gfpga_pad_IO_F2A[5]" x="2" y="0" z="3"/>
<io pad="gfpga_pad_IO_A2F[6]" x="2" y="0" z="4"/>
<io pad="gfpga_pad_IO_F2A[6]" x="2" y="0" z="5"/>
<io pad="gfpga_pad_IO_A2F[7]" x="2" y="0" z="6"/>
<io pad="gfpga_pad_IO_F2A[7]" x="2" y="0" z="7"/>
</io_coordinates>

136
openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_map.xml
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@ -1,136 +0,0 @@
<!--
- FPGA Fabric I/O Information
- Generated by OpenFPGA
- Date: Thu Jul 28 11:57:11 2022
-->
<io_coordinates>
<io pad="gfpga_pad_GPIO_PAD[96]" x="0" y="1" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[97]" x="0" y="1" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[98]" x="0" y="1" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[99]" x="0" y="1" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[100]" x="0" y="1" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[101]" x="0" y="1" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[102]" x="0" y="1" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[103]" x="0" y="1" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[104]" x="0" y="2" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[105]" x="0" y="2" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[106]" x="0" y="2" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[107]" x="0" y="2" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[108]" x="0" y="2" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[109]" x="0" y="2" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[110]" x="0" y="2" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[111]" x="0" y="2" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[112]" x="0" y="3" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[113]" x="0" y="3" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[114]" x="0" y="3" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[115]" x="0" y="3" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[116]" x="0" y="3" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[117]" x="0" y="3" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[118]" x="0" y="3" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[119]" x="0" y="3" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[120]" x="0" y="4" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[121]" x="0" y="4" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[122]" x="0" y="4" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[123]" x="0" y="4" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[124]" x="0" y="4" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[125]" x="0" y="4" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[126]" x="0" y="4" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[127]" x="0" y="4" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[88]" x="1" y="0" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[89]" x="1" y="0" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[90]" x="1" y="0" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[91]" x="1" y="0" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[92]" x="1" y="0" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[93]" x="1" y="0" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[94]" x="1" y="0" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[95]" x="1" y="0" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[0]" x="1" y="5" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[1]" x="1" y="5" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[2]" x="1" y="5" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[3]" x="1" y="5" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[4]" x="1" y="5" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[5]" x="1" y="5" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[6]" x="1" y="5" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[7]" x="1" y="5" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[80]" x="2" y="0" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[81]" x="2" y="0" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[82]" x="2" y="0" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[83]" x="2" y="0" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[84]" x="2" y="0" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[85]" x="2" y="0" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[86]" x="2" y="0" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[87]" x="2" y="0" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[8]" x="2" y="5" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[9]" x="2" y="5" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[10]" x="2" y="5" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[11]" x="2" y="5" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[12]" x="2" y="5" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[13]" x="2" y="5" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[14]" x="2" y="5" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[15]" x="2" y="5" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[72]" x="3" y="0" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[73]" x="3" y="0" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[74]" x="3" y="0" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[75]" x="3" y="0" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[76]" x="3" y="0" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[77]" x="3" y="0" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[78]" x="3" y="0" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[79]" x="3" y="0" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[16]" x="3" y="5" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[17]" x="3" y="5" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[18]" x="3" y="5" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[19]" x="3" y="5" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[20]" x="3" y="5" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[21]" x="3" y="5" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[22]" x="3" y="5" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[23]" x="3" y="5" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[64]" x="4" y="0" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[65]" x="4" y="0" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[66]" x="4" y="0" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[67]" x="4" y="0" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[68]" x="4" y="0" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[69]" x="4" y="0" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[70]" x="4" y="0" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[71]" x="4" y="0" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[24]" x="4" y="5" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[25]" x="4" y="5" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[26]" x="4" y="5" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[27]" x="4" y="5" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[28]" x="4" y="5" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[29]" x="4" y="5" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[30]" x="4" y="5" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[31]" x="4" y="5" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[56]" x="5" y="1" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[57]" x="5" y="1" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[58]" x="5" y="1" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[59]" x="5" y="1" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[60]" x="5" y="1" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[61]" x="5" y="1" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[62]" x="5" y="1" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[63]" x="5" y="1" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[48]" x="5" y="2" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[49]" x="5" y="2" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[50]" x="5" y="2" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[51]" x="5" y="2" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[52]" x="5" y="2" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[53]" x="5" y="2" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[54]" x="5" y="2" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[55]" x="5" y="2" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[40]" x="5" y="3" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[41]" x="5" y="3" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[42]" x="5" y="3" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[43]" x="5" y="3" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[44]" x="5" y="3" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[45]" x="5" y="3" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[46]" x="5" y="3" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[47]" x="5" y="3" z="7"/>
<io pad="gfpga_pad_GPIO_PAD[32]" x="5" y="4" z="0"/>
<io pad="gfpga_pad_GPIO_PAD[33]" x="5" y="4" z="1"/>
<io pad="gfpga_pad_GPIO_PAD[34]" x="5" y="4" z="2"/>
<io pad="gfpga_pad_GPIO_PAD[35]" x="5" y="4" z="3"/>
<io pad="gfpga_pad_GPIO_PAD[36]" x="5" y="4" z="4"/>
<io pad="gfpga_pad_GPIO_PAD[37]" x="5" y="4" z="5"/>
<io pad="gfpga_pad_GPIO_PAD[38]" x="5" y="4" z="6"/>
<io pad="gfpga_pad_GPIO_PAD[39]" x="5" y="4" z="7"/>
</io_coordinates>

28
openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv
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@ -1,17 +1,17 @@
orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,,
TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,,
TOP,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[1],,,
TOP,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[1],,,
TOP,,,,gfpga_pad_IO_A2F[8],pad_fpga_io[2],,,
TOP,,,,gfpga_pad_IO_F2A[8],pad_fpga_io[2],,,
TOP,,,,gfpga_pad_IO_A2F[31],pad_fpga_io[3],,,
TOP,,,,gfpga_pad_IO_F2A[31],pad_fpga_io[3],,,
RIGHT,,,,gfpga_pad_IO_A2F[32],pad_fpga_io[4],,,
RIGHT,,,,gfpga_pad_IO_F2A[32],pad_fpga_io[4],,,
RIGHT,,,,gfpga_pad_IO_A2F[40],pad_fpga_io[5],,,
RIGHT,,,,gfpga_pad_IO_F2A[40],pad_fpga_io[5],,,
BOTTOM,,,,gfpga_pad_IO_A2F[64],pad_fpga_io[6],,,
BOTTOM,,,,gfpga_pad_IO_F2A[64],pad_fpga_io[6],,,
LEFT,,,,gfpga_pad_IO_F2A[127],pad_fpga_io[7],,,
LEFT,,,,gfpga_pad_IO_A2F[127],pad_fpga_io[7],,,
TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,,
TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,,
TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,,
TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,,
TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,,
TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,,
RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,,
RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,,
RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,,
RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,,
BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,,
BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,,
LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,,
LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,,

1 orientation row col pin_num_in_cell port_name mapped_pin GPIO_type Associated Clock Clock Edge
2 TOP gfpga_pad_IO_A2F[0] pad_fpga_io[0]
3 TOP gfpga_pad_IO_F2A[0] pad_fpga_io[0]
4 TOP gfpga_pad_IO_A2F[4] gfpga_pad_IO_A2F[2] pad_fpga_io[1]
5 TOP gfpga_pad_IO_F2A[4] gfpga_pad_IO_F2A[2] pad_fpga_io[1]
6 TOP gfpga_pad_IO_A2F[8] gfpga_pad_IO_A2F[1] pad_fpga_io[2]
7 TOP gfpga_pad_IO_F2A[8] gfpga_pad_IO_F2A[1] pad_fpga_io[2]
8 TOP gfpga_pad_IO_A2F[31] gfpga_pad_IO_A2F[3] pad_fpga_io[3]
9 TOP gfpga_pad_IO_F2A[31] gfpga_pad_IO_F2A[3] pad_fpga_io[3]
10 RIGHT gfpga_pad_IO_A2F[32] gfpga_pad_IO_A2F[5] pad_fpga_io[4]
11 RIGHT gfpga_pad_IO_F2A[32] gfpga_pad_IO_F2A[5] pad_fpga_io[4]
12 RIGHT gfpga_pad_IO_A2F[40] gfpga_pad_IO_A2F[4] pad_fpga_io[5]
13 RIGHT gfpga_pad_IO_F2A[40] gfpga_pad_IO_F2A[4] pad_fpga_io[5]
14 BOTTOM gfpga_pad_IO_A2F[64] gfpga_pad_IO_A2F[6] pad_fpga_io[6]
15 BOTTOM gfpga_pad_IO_F2A[64] gfpga_pad_IO_F2A[6] pad_fpga_io[6]
16 LEFT gfpga_pad_IO_F2A[127] gfpga_pad_IO_F2A[7] pad_fpga_io[7]
17 LEFT gfpga_pad_IO_A2F[127] gfpga_pad_IO_A2F[7] pad_fpga_io[7]

2
openfpga_flow/tasks/basic_tests/constrain_pin_location/config/task.conf
View File

@ -22,7 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
openfpga_vpr_device_layout=4x4
openfpga_vpr_route_chan_width=20
openfpga_pcf=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf
openfpga_io_map_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_map.xml
openfpga_io_map_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml
openfpga_pin_table=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv
openfpga_vpr_fix_pins_file=and2_fix_pins.place