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[Test] Update pin constraints for different counter benchmarks

This commit is contained in:
tangxifan 2022-02-14 15:28:03 -08:00
parent 34e192c5ca
commit 7ef808cbe4
2 changed files with 8 additions and 1 deletions
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7
openfpga_flow/tasks/benchmark_sweep/counter8/config/pin_constraints_rst.xml Normal file
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@ -0,0 +1,7 @@
<pin_constraints>
<!-- For a given .blif file, we want to assign
- the reset signal to the op_reset[0] port of the FPGA fabric
-->
<set_io pin="op_reset[0]" net="rst_counter"/>
</pin_constraints>

2
openfpga_flow/tasks/benchmark_sweep/counter8/config/task.conf
View File

@ -41,7 +41,7 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = counter
bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml
bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_rst.xml
bench1_top = counter
bench1_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml