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[FPGA-Verilog] Fixed a bug on wiring FPGA global ports

This commit is contained in:
tangxifan 2022-02-14 15:21:29 -08:00
parent 570c1b10dc
commit 34e192c5ca
1 changed files with 3 additions and 1 deletions
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4
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
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@ -185,13 +185,15 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
/* For other ports, give an default value */
for (size_t pin_id = 0; pin_id < module_global_port.pins().size(); ++pin_id) {
BasicPort module_global_pin(module_global_port.get_name() + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
BasicPort module_global_pin(module_global_port.get_name(),
module_global_port.pins()[pin_id],
module_global_port.pins()[pin_id]);
/* If the global port name is in the pin constraints, we should wire it to the constrained pin */
std::string constrained_net_name = pin_constraints.pin_net(module_global_pin);
module_global_pin.set_name(module_global_port.get_name() + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX));
/* - If constrained to a given net in the benchmark, we connect the global pin to the net
* - If constrained to an open net in the benchmark, we assign it to a default value
*/