[script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment
This commit is contained in:
tangxifan
parent
baac236ed7
commit
b532bca9d2
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@ -50,7 +50,7 @@ module and2_top_formal_verification_random_tb;
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initial begin
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clk[0] <= 1'b0;
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while(1) begin
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#0.4537859857
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#0.5744515657
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clk[0] <= !clk[0];
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end
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end
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@ -109,7 +109,7 @@ initial begin
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$timeformat(-9, 2, "ns", 20);
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$display("Simulation start");
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// ----- Can be changed by the user for his/her need -------
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#6.353003979
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#8.042322159
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if(nb_error == 0) begin
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$display("Simulation Succeed");
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end else begin
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@ -9,27 +9,29 @@
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##################################################
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# Create clock
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##################################################
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create_clock clk[0] -period 9.07571962e-10 -waveform {0 4.53785981e-10}
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create_clock clk[0] -period 1.148903084e-09 -waveform {0 5.744515419e-10}
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##################################################
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# Create input and output delays for used I/Os
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##################################################
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set_input_delay -clock clk[0] -max 9.07571962e-10 gfpga_pad_GPIO_PAD[6]
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set_input_delay -clock clk[0] -max 9.07571962e-10 gfpga_pad_GPIO_PAD[1]
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set_output_delay -clock clk[0] -max 9.07571962e-10 gfpga_pad_GPIO_PAD[9]
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set_input_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[26]
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set_input_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[25]
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set_output_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[11]
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##################################################
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# Disable timing for unused I/Os
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##################################################
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set_disable_timing gfpga_pad_GPIO_PAD[0]
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set_disable_timing gfpga_pad_GPIO_PAD[1]
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set_disable_timing gfpga_pad_GPIO_PAD[2]
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set_disable_timing gfpga_pad_GPIO_PAD[3]
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set_disable_timing gfpga_pad_GPIO_PAD[4]
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set_disable_timing gfpga_pad_GPIO_PAD[5]
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set_disable_timing gfpga_pad_GPIO_PAD[6]
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set_disable_timing gfpga_pad_GPIO_PAD[7]
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set_disable_timing gfpga_pad_GPIO_PAD[8]
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set_disable_timing gfpga_pad_GPIO_PAD[9]
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set_disable_timing gfpga_pad_GPIO_PAD[10]
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set_disable_timing gfpga_pad_GPIO_PAD[11]
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set_disable_timing gfpga_pad_GPIO_PAD[12]
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set_disable_timing gfpga_pad_GPIO_PAD[13]
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set_disable_timing gfpga_pad_GPIO_PAD[14]
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@ -43,8 +45,6 @@ set_disable_timing gfpga_pad_GPIO_PAD[21]
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set_disable_timing gfpga_pad_GPIO_PAD[22]
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set_disable_timing gfpga_pad_GPIO_PAD[23]
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set_disable_timing gfpga_pad_GPIO_PAD[24]
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set_disable_timing gfpga_pad_GPIO_PAD[25]
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set_disable_timing gfpga_pad_GPIO_PAD[26]
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set_disable_timing gfpga_pad_GPIO_PAD[27]
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set_disable_timing gfpga_pad_GPIO_PAD[28]
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set_disable_timing gfpga_pad_GPIO_PAD[29]
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@ -160,7 +160,6 @@ set_disable_timing cbx_1__0_/chanx_left_in[9]
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set_disable_timing cbx_1__0_/chanx_right_in[9]
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set_disable_timing cbx_1__0_/chanx_left_in[10]
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set_disable_timing cbx_1__0_/chanx_right_in[10]
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set_disable_timing cbx_1__0_/chanx_left_in[11]
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set_disable_timing cbx_1__0_/chanx_right_in[11]
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set_disable_timing cbx_1__0_/chanx_left_in[12]
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set_disable_timing cbx_1__0_/chanx_right_in[12]
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@ -186,7 +185,6 @@ set_disable_timing cbx_1__0_/chanx_left_out[9]
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set_disable_timing cbx_1__0_/chanx_right_out[9]
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set_disable_timing cbx_1__0_/chanx_left_out[10]
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set_disable_timing cbx_1__0_/chanx_right_out[10]
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set_disable_timing cbx_1__0_/chanx_left_out[11]
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set_disable_timing cbx_1__0_/chanx_right_out[11]
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set_disable_timing cbx_1__0_/chanx_left_out[12]
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set_disable_timing cbx_1__0_/chanx_right_out[12]
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@ -272,7 +270,7 @@ set_disable_timing cbx_1__0_/mux_top_ipin_3/in[4]
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##################################################
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set_disable_timing cbx_1__1_/chanx_left_in[0]
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set_disable_timing cbx_1__1_/chanx_right_in[0]
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set_disable_timing cbx_1__1_/chanx_right_in[1]
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set_disable_timing cbx_1__1_/chanx_left_in[1]
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set_disable_timing cbx_1__1_/chanx_left_in[2]
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set_disable_timing cbx_1__1_/chanx_right_in[2]
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set_disable_timing cbx_1__1_/chanx_left_in[3]
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@ -294,9 +292,10 @@ set_disable_timing cbx_1__1_/chanx_right_in[10]
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set_disable_timing cbx_1__1_/chanx_left_in[11]
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set_disable_timing cbx_1__1_/chanx_right_in[11]
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set_disable_timing cbx_1__1_/chanx_left_in[12]
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set_disable_timing cbx_1__1_/chanx_right_in[12]
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set_disable_timing cbx_1__1_/chanx_left_out[0]
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set_disable_timing cbx_1__1_/chanx_right_out[0]
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set_disable_timing cbx_1__1_/chanx_right_out[1]
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set_disable_timing cbx_1__1_/chanx_left_out[1]
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set_disable_timing cbx_1__1_/chanx_left_out[2]
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set_disable_timing cbx_1__1_/chanx_right_out[2]
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set_disable_timing cbx_1__1_/chanx_left_out[3]
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@ -318,6 +317,7 @@ set_disable_timing cbx_1__1_/chanx_right_out[10]
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set_disable_timing cbx_1__1_/chanx_left_out[11]
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set_disable_timing cbx_1__1_/chanx_right_out[11]
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set_disable_timing cbx_1__1_/chanx_left_out[12]
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set_disable_timing cbx_1__1_/chanx_right_out[12]
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set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0]
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set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0]
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set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0]
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@ -326,6 +326,7 @@ set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_out
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set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0]
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set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0]
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set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0]
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set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0]
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set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0]
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set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0]
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set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[1]
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@ -336,6 +337,7 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[0]
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set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[0]
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set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[3]
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set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[1]
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set_disable_timing cbx_1__1_/mux_top_ipin_0/in[1]
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set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[2]
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set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[0]
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set_disable_timing cbx_1__1_/mux_top_ipin_0/in[0]
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@ -396,9 +398,7 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[4]
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##################################################
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# Disable timing for Connection block cby_0__1_
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##################################################
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set_disable_timing cby_0__1_/chany_bottom_in[0]
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set_disable_timing cby_0__1_/chany_top_in[0]
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set_disable_timing cby_0__1_/chany_bottom_in[1]
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set_disable_timing cby_0__1_/chany_top_in[1]
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set_disable_timing cby_0__1_/chany_bottom_in[2]
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set_disable_timing cby_0__1_/chany_top_in[2]
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@ -417,13 +417,11 @@ set_disable_timing cby_0__1_/chany_top_in[8]
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set_disable_timing cby_0__1_/chany_bottom_in[9]
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set_disable_timing cby_0__1_/chany_top_in[9]
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set_disable_timing cby_0__1_/chany_bottom_in[10]
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set_disable_timing cby_0__1_/chany_top_in[10]
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set_disable_timing cby_0__1_/chany_bottom_in[11]
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set_disable_timing cby_0__1_/chany_top_in[11]
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set_disable_timing cby_0__1_/chany_bottom_in[12]
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set_disable_timing cby_0__1_/chany_bottom_out[0]
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set_disable_timing cby_0__1_/chany_top_in[12]
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set_disable_timing cby_0__1_/chany_top_out[0]
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set_disable_timing cby_0__1_/chany_bottom_out[1]
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set_disable_timing cby_0__1_/chany_top_out[1]
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set_disable_timing cby_0__1_/chany_bottom_out[2]
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set_disable_timing cby_0__1_/chany_top_out[2]
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@ -442,11 +440,10 @@ set_disable_timing cby_0__1_/chany_top_out[8]
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set_disable_timing cby_0__1_/chany_bottom_out[9]
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set_disable_timing cby_0__1_/chany_top_out[9]
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set_disable_timing cby_0__1_/chany_bottom_out[10]
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set_disable_timing cby_0__1_/chany_top_out[10]
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set_disable_timing cby_0__1_/chany_bottom_out[11]
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set_disable_timing cby_0__1_/chany_top_out[11]
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set_disable_timing cby_0__1_/chany_bottom_out[12]
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set_disable_timing cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0]
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set_disable_timing cby_0__1_/chany_top_out[12]
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set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0]
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set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0]
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set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0]
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@ -455,13 +452,11 @@ set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_out
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set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0]
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set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0]
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set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0]
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set_disable_timing cby_0__1_/mux_left_ipin_0/in[1]
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set_disable_timing cby_0__1_/mux_left_ipin_1/in[1]
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set_disable_timing cby_0__1_/mux_right_ipin_5/in[1]
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set_disable_timing cby_0__1_/mux_left_ipin_0/in[0]
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set_disable_timing cby_0__1_/mux_left_ipin_1/in[0]
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set_disable_timing cby_0__1_/mux_right_ipin_5/in[0]
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set_disable_timing cby_0__1_/mux_left_ipin_1/in[3]
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set_disable_timing cby_0__1_/mux_right_ipin_0/in[1]
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set_disable_timing cby_0__1_/mux_right_ipin_6/in[1]
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set_disable_timing cby_0__1_/mux_left_ipin_1/in[2]
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@ -513,6 +508,7 @@ set_disable_timing cby_0__1_/mux_right_ipin_3/in[5]
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set_disable_timing cby_0__1_/mux_right_ipin_3/in[4]
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set_disable_timing cby_0__1_/mux_left_ipin_0/in[5]
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set_disable_timing cby_0__1_/mux_right_ipin_4/in[5]
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set_disable_timing cby_0__1_/mux_left_ipin_0/in[4]
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set_disable_timing cby_0__1_/mux_right_ipin_4/in[4]
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##################################################
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# Disable timing for Connection block cby_1__1_
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@ -520,7 +516,6 @@ set_disable_timing cby_0__1_/mux_right_ipin_4/in[4]
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set_disable_timing cby_1__1_/chany_top_in[0]
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set_disable_timing cby_1__1_/chany_bottom_in[1]
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set_disable_timing cby_1__1_/chany_top_in[1]
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set_disable_timing cby_1__1_/chany_bottom_in[2]
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set_disable_timing cby_1__1_/chany_top_in[2]
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set_disable_timing cby_1__1_/chany_bottom_in[3]
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set_disable_timing cby_1__1_/chany_top_in[3]
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@ -545,7 +540,6 @@ set_disable_timing cby_1__1_/chany_top_in[12]
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set_disable_timing cby_1__1_/chany_top_out[0]
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set_disable_timing cby_1__1_/chany_bottom_out[1]
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set_disable_timing cby_1__1_/chany_top_out[1]
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set_disable_timing cby_1__1_/chany_bottom_out[2]
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set_disable_timing cby_1__1_/chany_top_out[2]
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set_disable_timing cby_1__1_/chany_bottom_out[3]
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set_disable_timing cby_1__1_/chany_top_out[3]
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@ -568,8 +562,8 @@ set_disable_timing cby_1__1_/chany_top_out[11]
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set_disable_timing cby_1__1_/chany_bottom_out[12]
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set_disable_timing cby_1__1_/chany_top_out[12]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0]
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@ -578,6 +572,7 @@ set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1
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set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0]
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set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0]
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set_disable_timing cby_1__1_/mux_left_ipin_0/in[1]
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set_disable_timing cby_1__1_/mux_left_ipin_1/in[1]
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set_disable_timing cby_1__1_/mux_left_ipin_7/in[1]
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set_disable_timing cby_1__1_/mux_left_ipin_0/in[0]
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set_disable_timing cby_1__1_/mux_left_ipin_1/in[0]
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@ -589,7 +584,6 @@ set_disable_timing cby_1__1_/mux_left_ipin_1/in[2]
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set_disable_timing cby_1__1_/mux_left_ipin_2/in[0]
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set_disable_timing cby_1__1_/mux_right_ipin_0/in[0]
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set_disable_timing cby_1__1_/mux_left_ipin_2/in[3]
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set_disable_timing cby_1__1_/mux_left_ipin_3/in[1]
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set_disable_timing cby_1__1_/mux_right_ipin_1/in[1]
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set_disable_timing cby_1__1_/mux_left_ipin_2/in[2]
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set_disable_timing cby_1__1_/mux_left_ipin_3/in[0]
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@ -645,9 +639,7 @@ set_disable_timing cby_1__1_/mux_left_ipin_6/in[4]
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##################################################
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# Disable timing for Switch block sb_0__0_
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##################################################
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set_disable_timing sb_0__0_/chany_top_out[0]
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set_disable_timing sb_0__0_/chany_top_in[0]
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set_disable_timing sb_0__0_/chany_top_out[1]
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set_disable_timing sb_0__0_/chany_top_in[1]
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set_disable_timing sb_0__0_/chany_top_out[2]
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set_disable_timing sb_0__0_/chany_top_in[2]
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@ -666,10 +658,10 @@ set_disable_timing sb_0__0_/chany_top_in[8]
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set_disable_timing sb_0__0_/chany_top_out[9]
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set_disable_timing sb_0__0_/chany_top_in[9]
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set_disable_timing sb_0__0_/chany_top_out[10]
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set_disable_timing sb_0__0_/chany_top_in[10]
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set_disable_timing sb_0__0_/chany_top_out[11]
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set_disable_timing sb_0__0_/chany_top_in[11]
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set_disable_timing sb_0__0_/chany_top_out[12]
|
||||
set_disable_timing sb_0__0_/chany_top_in[12]
|
||||
set_disable_timing sb_0__0_/chanx_right_out[0]
|
||||
set_disable_timing sb_0__0_/chanx_right_in[0]
|
||||
set_disable_timing sb_0__0_/chanx_right_out[1]
|
||||
|
|
@ -692,13 +684,10 @@ set_disable_timing sb_0__0_/chanx_right_out[9]
|
|||
set_disable_timing sb_0__0_/chanx_right_in[9]
|
||||
set_disable_timing sb_0__0_/chanx_right_out[10]
|
||||
set_disable_timing sb_0__0_/chanx_right_in[10]
|
||||
set_disable_timing sb_0__0_/chanx_right_out[11]
|
||||
set_disable_timing sb_0__0_/chanx_right_in[11]
|
||||
set_disable_timing sb_0__0_/chanx_right_out[12]
|
||||
set_disable_timing sb_0__0_/chanx_right_in[12]
|
||||
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0]
|
||||
|
|
@ -717,10 +706,8 @@ set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pi
|
|||
set_disable_timing sb_0__0_/mux_top_track_0/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_12/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_24/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_0/in[1]
|
||||
set_disable_timing sb_0__0_/mux_top_track_2/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_14/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_2/in[1]
|
||||
set_disable_timing sb_0__0_/mux_top_track_4/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_16/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_4/in[1]
|
||||
|
|
@ -776,7 +763,6 @@ set_disable_timing sb_0__0_/mux_right_track_14/in[0]
|
|||
set_disable_timing sb_0__0_/mux_right_track_16/in[0]
|
||||
set_disable_timing sb_0__0_/mux_right_track_18/in[0]
|
||||
set_disable_timing sb_0__0_/mux_right_track_20/in[0]
|
||||
set_disable_timing sb_0__0_/mux_right_track_22/in[0]
|
||||
set_disable_timing sb_0__0_/mux_right_track_24/in[0]
|
||||
set_disable_timing sb_0__0_/mux_right_track_0/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_24/in[2]
|
||||
|
|
@ -797,7 +783,7 @@ set_disable_timing sb_0__0_/mux_top_track_22/in[1]
|
|||
##################################################
|
||||
set_disable_timing sb_0__1_/chanx_right_out[0]
|
||||
set_disable_timing sb_0__1_/chanx_right_in[0]
|
||||
set_disable_timing sb_0__1_/chanx_right_in[1]
|
||||
set_disable_timing sb_0__1_/chanx_right_out[1]
|
||||
set_disable_timing sb_0__1_/chanx_right_out[2]
|
||||
set_disable_timing sb_0__1_/chanx_right_in[2]
|
||||
set_disable_timing sb_0__1_/chanx_right_out[3]
|
||||
|
|
@ -819,9 +805,8 @@ set_disable_timing sb_0__1_/chanx_right_in[10]
|
|||
set_disable_timing sb_0__1_/chanx_right_out[11]
|
||||
set_disable_timing sb_0__1_/chanx_right_in[11]
|
||||
set_disable_timing sb_0__1_/chanx_right_out[12]
|
||||
set_disable_timing sb_0__1_/chany_bottom_in[0]
|
||||
set_disable_timing sb_0__1_/chanx_right_in[12]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[0]
|
||||
set_disable_timing sb_0__1_/chany_bottom_in[1]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[1]
|
||||
set_disable_timing sb_0__1_/chany_bottom_in[2]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[2]
|
||||
|
|
@ -840,21 +825,21 @@ set_disable_timing sb_0__1_/chany_bottom_out[8]
|
|||
set_disable_timing sb_0__1_/chany_bottom_in[9]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[9]
|
||||
set_disable_timing sb_0__1_/chany_bottom_in[10]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[10]
|
||||
set_disable_timing sb_0__1_/chany_bottom_in[11]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[11]
|
||||
set_disable_timing sb_0__1_/chany_bottom_in[12]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[12]
|
||||
set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0]
|
||||
set_disable_timing sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0]
|
||||
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0]
|
||||
|
|
@ -864,6 +849,7 @@ set_disable_timing sb_0__1_/mux_right_track_0/in[0]
|
|||
set_disable_timing sb_0__1_/mux_right_track_12/in[0]
|
||||
set_disable_timing sb_0__1_/mux_right_track_24/in[0]
|
||||
set_disable_timing sb_0__1_/mux_right_track_0/in[1]
|
||||
set_disable_timing sb_0__1_/mux_right_track_2/in[0]
|
||||
set_disable_timing sb_0__1_/mux_right_track_14/in[0]
|
||||
set_disable_timing sb_0__1_/mux_right_track_2/in[1]
|
||||
set_disable_timing sb_0__1_/mux_right_track_4/in[0]
|
||||
|
|
@ -910,7 +896,6 @@ set_disable_timing sb_0__1_/mux_bottom_track_3/in[3]
|
|||
set_disable_timing sb_0__1_/mux_bottom_track_15/in[3]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_17/in[2]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_23/in[0]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_21/in[0]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_19/in[0]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_17/in[0]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_15/in[0]
|
||||
|
|
@ -921,6 +906,7 @@ set_disable_timing sb_0__1_/mux_bottom_track_7/in[0]
|
|||
set_disable_timing sb_0__1_/mux_bottom_track_5/in[0]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_3/in[0]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_1/in[0]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_25/in[0]
|
||||
set_disable_timing sb_0__1_/mux_right_track_22/in[1]
|
||||
set_disable_timing sb_0__1_/mux_right_track_20/in[1]
|
||||
set_disable_timing sb_0__1_/mux_right_track_18/in[1]
|
||||
|
|
@ -940,7 +926,6 @@ set_disable_timing sb_0__1_/mux_right_track_24/in[2]
|
|||
set_disable_timing sb_1__0_/chany_top_in[0]
|
||||
set_disable_timing sb_1__0_/chany_top_out[1]
|
||||
set_disable_timing sb_1__0_/chany_top_in[1]
|
||||
set_disable_timing sb_1__0_/chany_top_out[2]
|
||||
set_disable_timing sb_1__0_/chany_top_in[2]
|
||||
set_disable_timing sb_1__0_/chany_top_out[3]
|
||||
set_disable_timing sb_1__0_/chany_top_in[3]
|
||||
|
|
@ -984,7 +969,6 @@ set_disable_timing sb_1__0_/chanx_left_in[9]
|
|||
set_disable_timing sb_1__0_/chanx_left_out[9]
|
||||
set_disable_timing sb_1__0_/chanx_left_in[10]
|
||||
set_disable_timing sb_1__0_/chanx_left_out[10]
|
||||
set_disable_timing sb_1__0_/chanx_left_in[11]
|
||||
set_disable_timing sb_1__0_/chanx_left_out[11]
|
||||
set_disable_timing sb_1__0_/chanx_left_in[12]
|
||||
set_disable_timing sb_1__0_/chanx_left_out[12]
|
||||
|
|
@ -1080,7 +1064,6 @@ set_disable_timing sb_1__0_/mux_top_track_12/in[2]
|
|||
set_disable_timing sb_1__0_/mux_top_track_10/in[2]
|
||||
set_disable_timing sb_1__0_/mux_top_track_8/in[2]
|
||||
set_disable_timing sb_1__0_/mux_top_track_6/in[2]
|
||||
set_disable_timing sb_1__0_/mux_top_track_4/in[2]
|
||||
set_disable_timing sb_1__0_/mux_top_track_2/in[3]
|
||||
##################################################
|
||||
# Disable timing for Switch block sb_1__1_
|
||||
|
|
@ -1088,7 +1071,6 @@ set_disable_timing sb_1__0_/mux_top_track_2/in[3]
|
|||
set_disable_timing sb_1__1_/chany_bottom_out[0]
|
||||
set_disable_timing sb_1__1_/chany_bottom_in[1]
|
||||
set_disable_timing sb_1__1_/chany_bottom_out[1]
|
||||
set_disable_timing sb_1__1_/chany_bottom_in[2]
|
||||
set_disable_timing sb_1__1_/chany_bottom_out[2]
|
||||
set_disable_timing sb_1__1_/chany_bottom_in[3]
|
||||
set_disable_timing sb_1__1_/chany_bottom_out[3]
|
||||
|
|
@ -1112,7 +1094,7 @@ set_disable_timing sb_1__1_/chany_bottom_in[12]
|
|||
set_disable_timing sb_1__1_/chany_bottom_out[12]
|
||||
set_disable_timing sb_1__1_/chanx_left_in[0]
|
||||
set_disable_timing sb_1__1_/chanx_left_out[0]
|
||||
set_disable_timing sb_1__1_/chanx_left_out[1]
|
||||
set_disable_timing sb_1__1_/chanx_left_in[1]
|
||||
set_disable_timing sb_1__1_/chanx_left_in[2]
|
||||
set_disable_timing sb_1__1_/chanx_left_out[2]
|
||||
set_disable_timing sb_1__1_/chanx_left_in[3]
|
||||
|
|
@ -1134,6 +1116,7 @@ set_disable_timing sb_1__1_/chanx_left_out[10]
|
|||
set_disable_timing sb_1__1_/chanx_left_in[11]
|
||||
set_disable_timing sb_1__1_/chanx_left_out[11]
|
||||
set_disable_timing sb_1__1_/chanx_left_in[12]
|
||||
set_disable_timing sb_1__1_/chanx_left_out[12]
|
||||
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0]
|
||||
|
|
@ -1143,10 +1126,12 @@ set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__p
|
|||
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0]
|
||||
set_disable_timing sb_1__1_/mux_bottom_track_1/in[0]
|
||||
|
|
@ -1194,11 +1179,11 @@ set_disable_timing sb_1__1_/mux_left_track_11/in[1]
|
|||
set_disable_timing sb_1__1_/mux_left_track_23/in[1]
|
||||
set_disable_timing sb_1__1_/mux_left_track_11/in[2]
|
||||
set_disable_timing sb_1__1_/mux_left_track_13/in[2]
|
||||
set_disable_timing sb_1__1_/mux_left_track_25/in[2]
|
||||
set_disable_timing sb_1__1_/mux_left_track_1/in[3]
|
||||
set_disable_timing sb_1__1_/mux_left_track_13/in[3]
|
||||
set_disable_timing sb_1__1_/mux_left_track_15/in[2]
|
||||
set_disable_timing sb_1__1_/mux_left_track_17/in[2]
|
||||
set_disable_timing sb_1__1_/mux_left_track_3/in[0]
|
||||
set_disable_timing sb_1__1_/mux_left_track_5/in[0]
|
||||
set_disable_timing sb_1__1_/mux_left_track_7/in[0]
|
||||
set_disable_timing sb_1__1_/mux_left_track_9/in[0]
|
||||
|
|
@ -1233,12 +1218,12 @@ set_disable_timing sb_1__1_/mux_bottom_track_23/in[1]
|
|||
#######################################
|
||||
# Disable unused pins for pb_graph_node clb[0]
|
||||
#######################################
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[0]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[1]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[2]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[4]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[5]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[6]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[7]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[8]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[9]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[0]
|
||||
|
|
@ -1248,9 +1233,9 @@ set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_clk[0]
|
|||
#######################################
|
||||
# Disable unused mux_inputs for pb_graph_node clb[0]
|
||||
#######################################
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[0]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[1]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6]
|
||||
|
|
@ -1466,20 +1451,16 @@ set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/*
|
|||
#######################################
|
||||
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/*
|
||||
#######################################
|
||||
# Disable Timing for unused resources in grid[1][2][1]
|
||||
# Disable Timing for unused grid[1][2][1]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node io[0]
|
||||
# Disable all the ports for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/io_outpad[0]
|
||||
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/*
|
||||
#######################################
|
||||
# Disable unused mux_inputs for pb_graph_node io[0]
|
||||
# Disable all the ports for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1//direct_interc_1_/in[0]
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
|
||||
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/*
|
||||
#######################################
|
||||
# Disable Timing for unused grid[1][2][2]
|
||||
#######################################
|
||||
|
|
@ -1525,20 +1506,16 @@ set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__5/*
|
|||
#######################################
|
||||
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/*
|
||||
#######################################
|
||||
# Disable Timing for unused resources in grid[1][2][6]
|
||||
# Disable Timing for unused grid[1][2][6]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node io[0]
|
||||
# Disable all the ports for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__6/io_outpad[0]
|
||||
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__6/*
|
||||
#######################################
|
||||
# Disable unused mux_inputs for pb_graph_node io[0]
|
||||
# Disable all the ports for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__6//direct_interc_1_/in[0]
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
|
||||
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/*
|
||||
#######################################
|
||||
# Disable Timing for unused grid[1][2][7]
|
||||
#######################################
|
||||
|
|
@ -1565,20 +1542,16 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__0/*
|
|||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/*
|
||||
#######################################
|
||||
# Disable Timing for unused resources in grid[2][1][1]
|
||||
# Disable Timing for unused grid[2][1][1]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node io[0]
|
||||
# Disable all the ports for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__1/io_inpad[0]
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__1/*
|
||||
#######################################
|
||||
# Disable unused mux_inputs for pb_graph_node io[0]
|
||||
# Disable all the ports for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__1//direct_interc_0_/in[0]
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/*
|
||||
#######################################
|
||||
# Disable Timing for unused grid[2][1][2]
|
||||
#######################################
|
||||
|
|
@ -1591,16 +1564,20 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/*
|
|||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/*
|
||||
#######################################
|
||||
# Disable Timing for unused grid[2][1][3]
|
||||
# Disable Timing for unused resources in grid[2][1][3]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable all the ports for pb_graph_node io[0]
|
||||
# Disable unused pins for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/*
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/io_inpad[0]
|
||||
#######################################
|
||||
# Disable all the ports for pb_graph_node iopad[0]
|
||||
# Disable unused mux_inputs for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/*
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3//direct_interc_0_/in[0]
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
|
||||
#######################################
|
||||
# Disable Timing for unused grid[2][1][4]
|
||||
#######################################
|
||||
|
|
@ -1751,27 +1728,35 @@ set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/*
|
|||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/*
|
||||
#######################################
|
||||
# Disable Timing for unused grid[0][1][1]
|
||||
# Disable Timing for unused resources in grid[0][1][1]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable all the ports for pb_graph_node io[0]
|
||||
# Disable unused pins for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/*
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/io_outpad[0]
|
||||
#######################################
|
||||
# Disable all the ports for pb_graph_node iopad[0]
|
||||
# Disable unused mux_inputs for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/*
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1//direct_interc_1_/in[0]
|
||||
#######################################
|
||||
# Disable Timing for unused grid[0][1][2]
|
||||
# Disable unused pins for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
|
||||
#######################################
|
||||
# Disable Timing for unused resources in grid[0][1][2]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable all the ports for pb_graph_node io[0]
|
||||
# Disable unused pins for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/*
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/io_outpad[0]
|
||||
#######################################
|
||||
# Disable all the ports for pb_graph_node iopad[0]
|
||||
# Disable unused mux_inputs for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/*
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2//direct_interc_1_/in[0]
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
|
||||
#######################################
|
||||
# Disable Timing for unused grid[0][1][3]
|
||||
#######################################
|
||||
|
|
|
|||
|
|
@ -42,25 +42,27 @@ wire [0:0] clk_fm;
|
|||
// ----- End Connect Global ports of FPGA top module -----
|
||||
|
||||
// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
|
||||
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[6] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[6] = a[0];
|
||||
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[26] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[26] = a[0];
|
||||
|
||||
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[1] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[1] = b[0];
|
||||
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[25] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[25] = b[0];
|
||||
|
||||
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[9] -----
|
||||
assign c[0] = gfpga_pad_GPIO_PAD_fm[9];
|
||||
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[11] -----
|
||||
assign c[0] = gfpga_pad_GPIO_PAD_fm[11];
|
||||
|
||||
// ----- Wire unused FPGA I/Os to constants -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[1] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[2] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[3] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[4] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[5] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[6] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[7] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0;
|
||||
|
|
@ -74,8 +76,6 @@ wire [0:0] clk_fm;
|
|||
assign gfpga_pad_GPIO_PAD_fm[22] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[23] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[24] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[25] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[26] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[27] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[28] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[29] = 1'b0;
|
||||
|
|
@ -125,14 +125,14 @@ initial begin
|
|||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b0011;
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b1100;
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b0001;
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b1110;
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0011;
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1100;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -151,12 +151,12 @@ initial begin
|
|||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -197,10 +197,10 @@ initial begin
|
|||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:2] = 3'b011;
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:2] = 3'b100;
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -245,14 +245,14 @@ initial begin
|
|||
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -295,18 +295,18 @@ initial begin
|
|||
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -381,8 +381,8 @@ initial begin
|
|||
force U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -403,8 +403,8 @@ initial begin
|
|||
force U0_formal_verification.sb_1__1_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_23.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_outb[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
@ -443,16 +443,16 @@ initial begin
|
|||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:2] = 3'b010;
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:2] = 3'b101;
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_out[0:2] = 3'b101;
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_outb[0:2] = 3'b010;
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
@ -471,12 +471,12 @@ initial begin
|
|||
force U0_formal_verification.cby_0__1_.mem_right_ipin_7.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
// Bitstream width (LSB -> MSB): 1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -158,12 +158,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
|
|
@ -259,6 +253,12 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
|
|
@ -294,17 +294,138 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -391,129 +512,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
|
|
@ -528,3 +526,5 @@
|
|||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
|
|
|
|||
|
|
@ -10,9 +10,9 @@
|
|||
</bit>
|
||||
<bit id="525" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="524" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]">
|
||||
<bit id="524" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="523" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
|
||||
<bit id="523" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="522" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -32,7 +32,7 @@
|
|||
</bit>
|
||||
<bit id="514" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="513" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
<bit id="513" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="512" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -320,11 +320,11 @@
|
|||
</bit>
|
||||
<bit id="370" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="369" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[2]">
|
||||
<bit id="369" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="368" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[1]">
|
||||
<bit id="368" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="367" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[0]">
|
||||
<bit id="367" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="366" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_2.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -332,11 +332,11 @@
|
|||
</bit>
|
||||
<bit id="364" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="363" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_1.mem_out[2]">
|
||||
<bit id="363" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="362" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_1.mem_out[1]">
|
||||
<bit id="362" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="361" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_1.mem_out[0]">
|
||||
<bit id="361" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="360" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_0.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -514,7 +514,7 @@
|
|||
</bit>
|
||||
<bit id="273" value="0" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="272" value="0" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[0]">
|
||||
<bit id="272" value="1" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="271" value="0" path="fpga_top.sb_1__0_.mem_top_track_2.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -592,25 +592,25 @@
|
|||
</bit>
|
||||
<bit id="234" value="0" path="fpga_top.cby_0__1_.mem_right_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="233" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_1.mem_out[2]">
|
||||
<bit id="233" value="1" path="fpga_top.cby_0__1_.mem_left_ipin_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="232" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="231" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_1.mem_out[0]">
|
||||
<bit id="231" value="1" path="fpga_top.cby_0__1_.mem_left_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="230" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_0.mem_out[2]">
|
||||
<bit id="230" value="1" path="fpga_top.cby_0__1_.mem_left_ipin_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="229" value="1" path="fpga_top.cby_0__1_.mem_left_ipin_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="228" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_0.mem_out[0]">
|
||||
<bit id="228" value="1" path="fpga_top.cby_0__1_.mem_left_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="227" value="0" path="fpga_top.sb_0__0_.mem_right_track_24.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="226" value="0" path="fpga_top.sb_0__0_.mem_right_track_24.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="225" value="0" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[1]">
|
||||
<bit id="225" value="1" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="224" value="0" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[0]">
|
||||
<bit id="224" value="1" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="223" value="0" path="fpga_top.sb_0__0_.mem_right_track_20.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -710,27 +710,27 @@
|
|||
</bit>
|
||||
<bit id="175" value="0" path="fpga_top.sb_0__0_.mem_top_track_4.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="174" value="0" path="fpga_top.sb_0__0_.mem_top_track_2.mem_out[1]">
|
||||
<bit id="174" value="1" path="fpga_top.sb_0__0_.mem_top_track_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="173" value="0" path="fpga_top.sb_0__0_.mem_top_track_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="172" value="0" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[2]">
|
||||
<bit id="172" value="1" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="171" value="0" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[1]">
|
||||
<bit id="171" value="1" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="170" value="0" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="169" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_25.mem_out[1]">
|
||||
<bit id="169" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_25.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="168" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_25.mem_out[0]">
|
||||
<bit id="168" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_25.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="167" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_23.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="166" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_23.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="165" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[1]">
|
||||
<bit id="165" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="164" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[0]">
|
||||
<bit id="164" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="163" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_19.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -824,9 +824,9 @@
|
|||
</bit>
|
||||
<bit id="118" value="0" path="fpga_top.sb_0__1_.mem_right_track_4.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="117" value="1" path="fpga_top.sb_0__1_.mem_right_track_2.mem_out[1]">
|
||||
<bit id="117" value="0" path="fpga_top.sb_0__1_.mem_right_track_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="116" value="1" path="fpga_top.sb_0__1_.mem_right_track_2.mem_out[0]">
|
||||
<bit id="116" value="0" path="fpga_top.sb_0__1_.mem_right_track_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="115" value="0" path="fpga_top.sb_0__1_.mem_right_track_0.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -862,11 +862,11 @@
|
|||
</bit>
|
||||
<bit id="99" value="0" path="fpga_top.cbx_1__1_.mem_top_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="98" value="1" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[2]">
|
||||
<bit id="98" value="0" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="97" value="1" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[1]">
|
||||
<bit id="97" value="0" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="96" value="1" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[0]">
|
||||
<bit id="96" value="0" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="95" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_7.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -918,7 +918,7 @@
|
|||
</bit>
|
||||
<bit id="71" value="0" path="fpga_top.sb_1__1_.mem_left_track_25.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="70" value="1" path="fpga_top.sb_1__1_.mem_left_track_25.mem_out[0]">
|
||||
<bit id="70" value="0" path="fpga_top.sb_1__1_.mem_left_track_25.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="69" value="0" path="fpga_top.sb_1__1_.mem_left_track_23.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -962,9 +962,9 @@
|
|||
</bit>
|
||||
<bit id="49" value="0" path="fpga_top.sb_1__1_.mem_left_track_5.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="48" value="0" path="fpga_top.sb_1__1_.mem_left_track_3.mem_out[1]">
|
||||
<bit id="48" value="1" path="fpga_top.sb_1__1_.mem_left_track_3.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="47" value="0" path="fpga_top.sb_1__1_.mem_left_track_3.mem_out[0]">
|
||||
<bit id="47" value="1" path="fpga_top.sb_1__1_.mem_left_track_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="46" value="0" path="fpga_top.sb_1__1_.mem_left_track_1.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -1036,11 +1036,11 @@
|
|||
</bit>
|
||||
<bit id="12" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="11" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
<bit id="11" value="0" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="10" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="9" value="0" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
<bit id="9" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="8" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
|
|
|
|||
|
|
@ -431,14 +431,14 @@
|
|||
<instance level="3" name="mem_fle_3_in_0"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="a"/>
|
||||
<path id="3" net_name="b"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
<path id="6" net_name="unmapped"/>
|
||||
<path id="7" net_name="unmapped"/>
|
||||
<path id="7" net_name="a"/>
|
||||
<path id="8" net_name="unmapped"/>
|
||||
<path id="9" net_name="unmapped"/>
|
||||
<path id="10" net_name="unmapped"/>
|
||||
|
|
@ -449,10 +449,10 @@
|
|||
<output_nets>
|
||||
<path id="0" net_name="a"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="3">
|
||||
<bitstream path_id="7">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
<bit memory_port="mem_out[3]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
|
|
@ -498,14 +498,14 @@
|
|||
<instance level="3" name="mem_fle_3_in_3"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="a"/>
|
||||
<path id="3" net_name="b"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
<path id="6" net_name="unmapped"/>
|
||||
<path id="7" net_name="unmapped"/>
|
||||
<path id="7" net_name="a"/>
|
||||
<path id="8" net_name="unmapped"/>
|
||||
<path id="9" net_name="unmapped"/>
|
||||
<path id="10" net_name="unmapped"/>
|
||||
|
|
@ -516,9 +516,9 @@
|
|||
<output_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bitstream path_id="3">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
<bit memory_port="mem_out[3]" value="1"/>
|
||||
</bitstream>
|
||||
|
|
@ -683,7 +683,7 @@
|
|||
<instance level="4" name="GPIO_DFF_mem"/>
|
||||
</hierarchy>
|
||||
<bitstream>
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
|
|
@ -715,7 +715,7 @@
|
|||
<instance level="4" name="GPIO_DFF_mem"/>
|
||||
</hierarchy>
|
||||
<bitstream>
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
|
|
@ -1054,17 +1054,17 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="1" net_name="b"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="b"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bitstream path_id="1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_top_track_2" hierarchy_level="2">
|
||||
|
|
@ -1074,16 +1074,16 @@
|
|||
<instance level="2" name="mem_top_track_2"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="1" net_name="a"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="a"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bitstream path_id="1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_top_track_4" hierarchy_level="2">
|
||||
|
|
@ -1093,7 +1093,7 @@
|
|||
<instance level="2" name="mem_top_track_4"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
|
|
@ -1190,7 +1190,7 @@
|
|||
<instance level="2" name="mem_top_track_14"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
|
|
@ -1209,7 +1209,7 @@
|
|||
<instance level="2" name="mem_top_track_16"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
|
|
@ -1301,7 +1301,7 @@
|
|||
<instance level="2" name="mem_right_track_0"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
|
|
@ -1516,15 +1516,15 @@
|
|||
<instance level="2" name="mem_right_track_22"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_right_track_24" hierarchy_level="2">
|
||||
|
|
@ -1556,7 +1556,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="b"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
|
|
@ -1576,16 +1576,16 @@
|
|||
<instance level="2" name="mem_right_track_2"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_right_track_4" hierarchy_level="2">
|
||||
|
|
@ -1653,7 +1653,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="a"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -1672,7 +1672,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="a"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
|
|
@ -1692,7 +1692,7 @@
|
|||
<instance level="2" name="mem_right_track_14"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
|
|
@ -1749,7 +1749,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="1" net_name="a"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -1767,7 +1767,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="1" net_name="b"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -1785,7 +1785,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="a"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -1826,7 +1826,7 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="b"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -1846,8 +1846,8 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="1" net_name="b"/>
|
||||
<path id="2" net_name="a"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -1865,7 +1865,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="1" net_name="a"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -1962,7 +1962,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="1" net_name="b"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -1981,7 +1981,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="1" net_name="a"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -1998,15 +1998,15 @@
|
|||
<instance level="2" name="mem_bottom_track_21"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_bottom_track_23" hierarchy_level="2">
|
||||
|
|
@ -2034,15 +2034,15 @@
|
|||
<instance level="2" name="mem_bottom_track_25"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
|
|
@ -2098,13 +2098,13 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="c"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bitstream path_id="2">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
|
|
@ -2560,7 +2560,7 @@
|
|||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="b"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -2807,7 +2807,7 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="b"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -2827,15 +2827,15 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="c"/>
|
||||
<path id="1" net_name="b"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_left_track_5" hierarchy_level="2">
|
||||
|
|
@ -2864,7 +2864,7 @@
|
|||
<instance level="2" name="mem_left_track_7"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
|
|
@ -2904,7 +2904,7 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="a"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -2923,7 +2923,7 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="a"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -2943,7 +2943,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="b"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -3036,13 +3036,13 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="a"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="2">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
|
|
@ -3174,7 +3174,7 @@
|
|||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="4" net_name="c"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -3315,7 +3315,7 @@
|
|||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="a"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -3335,8 +3335,8 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="b"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="c"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
|
|
@ -3356,8 +3356,8 @@
|
|||
<instance level="2" name="mem_bottom_ipin_2"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="c"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
|
|
@ -3453,7 +3453,7 @@
|
|||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="a"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -3494,20 +3494,20 @@
|
|||
<instance level="2" name="mem_top_ipin_0"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="c"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_top_ipin_1" hierarchy_level="2">
|
||||
|
|
@ -3565,20 +3565,20 @@
|
|||
<instance level="2" name="mem_left_ipin_0"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="a"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="0" net_name="b"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="5">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_left_ipin_1" hierarchy_level="2">
|
||||
|
|
@ -3588,20 +3588,20 @@
|
|||
<instance level="2" name="mem_left_ipin_1"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="a"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="a"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bitstream path_id="2">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_right_ipin_0" hierarchy_level="2">
|
||||
|
|
@ -3611,7 +3611,7 @@
|
|||
<instance level="2" name="mem_right_ipin_0"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
|
|
@ -3662,7 +3662,7 @@
|
|||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
<path id="5" net_name="c"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -3708,7 +3708,7 @@
|
|||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="a"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -3726,7 +3726,7 @@
|
|||
<instance level="2" name="mem_right_ipin_5"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
|
|
@ -3749,7 +3749,7 @@
|
|||
<instance level="2" name="mem_right_ipin_6"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
|
|
@ -3828,12 +3828,12 @@
|
|||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="c"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_left_ipin_2" hierarchy_level="2">
|
||||
|
|
@ -3845,7 +3845,7 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="c"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
|
|
@ -3866,7 +3866,7 @@
|
|||
<instance level="2" name="mem_left_ipin_3"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
|
|
@ -3874,12 +3874,12 @@
|
|||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_left_ipin_4" hierarchy_level="2">
|
||||
|
|
@ -4004,7 +4004,7 @@
|
|||
<instance level="2" name="mem_right_ipin_1"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ set_units -time s
|
|||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 9.07571962e-10 -waveform {0 4.53785981e-10} [get_ports {clk[0]}]
|
||||
create_clock -name clk[0] -period 1.148903084e-09 -waveform {0 5.744515419e-10} [get_ports {clk[0]}]
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
-->
|
||||
|
||||
<io_mapping>
|
||||
<io name="gfpga_pad_GPIO_PAD[6:6]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[1:1]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[9:9]" net="c" dir="output"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[26:26]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[25:25]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[11:11]" net="c" dir="output"/>
|
||||
</io_mapping>
|
||||
|
|
|
|||
|
|
@ -49,43 +49,43 @@ set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/c
|
|||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
|
|
|
|||
|
|
@ -37,8 +37,8 @@ set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/c
|
|||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
|
|
@ -49,41 +49,41 @@ set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/c
|
|||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
|
|
|
|||
|
|
@ -49,43 +49,43 @@ set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subti
|
|||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
|
|
|
|||
|
|
@ -37,8 +37,8 @@ set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/cha
|
|||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[9] 6.020400151e-11
|
||||
|
|
@ -49,41 +49,41 @@ set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/ch
|
|||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ module and2_top_formal_verification_random_tb;
|
|||
initial begin
|
||||
clk[0] <= 1'b0;
|
||||
while(1) begin
|
||||
#0.4537859857
|
||||
#0.5422864556
|
||||
clk[0] <= !clk[0];
|
||||
end
|
||||
end
|
||||
|
|
@ -109,7 +109,7 @@ initial begin
|
|||
$timeformat(-9, 2, "ns", 20);
|
||||
$display("Simulation start");
|
||||
// ----- Can be changed by the user for his/her need -------
|
||||
#6.353003979
|
||||
#7.592010975
|
||||
if(nb_error == 0) begin
|
||||
$display("Simulation Succeed");
|
||||
end else begin
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -42,14 +42,14 @@ wire [0:0] clk_fm;
|
|||
// ----- End Connect Global ports of FPGA top module -----
|
||||
|
||||
// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
|
||||
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[65] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[65] = a[0];
|
||||
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[13] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[13] = a[0];
|
||||
|
||||
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[71] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[71] = b[0];
|
||||
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[12] = b[0];
|
||||
|
||||
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[56] -----
|
||||
assign c[0] = gfpga_pad_GPIO_PAD_fm[56];
|
||||
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[10] -----
|
||||
assign c[0] = gfpga_pad_GPIO_PAD_fm[10];
|
||||
|
||||
// ----- Wire unused FPGA I/Os to constants -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
|
||||
|
|
@ -62,10 +62,7 @@ wire [0:0] clk_fm;
|
|||
assign gfpga_pad_GPIO_PAD_fm[7] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0;
|
||||
|
|
@ -108,6 +105,7 @@ wire [0:0] clk_fm;
|
|||
assign gfpga_pad_GPIO_PAD_fm[53] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[54] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[55] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[56] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[57] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[58] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[59] = 1'b0;
|
||||
|
|
@ -116,11 +114,13 @@ wire [0:0] clk_fm;
|
|||
assign gfpga_pad_GPIO_PAD_fm[62] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[63] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[64] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[65] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[66] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[67] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[68] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[69] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[70] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[71] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[72] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[73] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[74] = 1'b0;
|
||||
|
|
@ -529,10 +529,10 @@ initial begin
|
|||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000;
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111;
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -557,14 +557,14 @@ initial begin
|
|||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b1101;
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b0010;
|
||||
force U0_formal_verification.grid_clb_3__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
|
||||
force U0_formal_verification.grid_clb_3__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
|
||||
force U0_formal_verification.grid_clb_3__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -769,10 +769,10 @@ initial begin
|
|||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000;
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111;
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -797,14 +797,14 @@ initial begin
|
|||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b0001;
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b1110;
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0011;
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1100;
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -969,8 +969,8 @@ initial begin
|
|||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -1061,8 +1061,8 @@ initial begin
|
|||
force U0_formal_verification.grid_io_right_5__2_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_5__2_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_5__2_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_5__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_5__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_5__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_5__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_5__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_5__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_5__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -1241,8 +1241,8 @@ initial begin
|
|||
force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:3] = 4'b0011;
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:3] = 4'b1100;
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -1337,8 +1337,8 @@ initial begin
|
|||
force U0_formal_verification.sb_0__4_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_10.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_14.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1531,8 +1531,8 @@ initial begin
|
|||
force U0_formal_verification.sb_2__1_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_out[0:3] = 4'b0111;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_outb[0:3] = 4'b1000;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -1593,8 +1593,8 @@ initial begin
|
|||
force U0_formal_verification.sb_2__4_.mem_right_track_16.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_1.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1613,18 +1613,18 @@ initial begin
|
|||
force U0_formal_verification.sb_2__4_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_out[0:3] = 4'b0010;
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_outb[0:3] = 4'b1101;
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_out[0:3] = 4'b0010;
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_outb[0:3] = 4'b1101;
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_2.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_2.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_10.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_18.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
@ -1745,8 +1745,8 @@ initial begin
|
|||
force U0_formal_verification.sb_3__4_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__4_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_3__4_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_0.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_0.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_0.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_0.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1767,8 +1767,8 @@ initial begin
|
|||
force U0_formal_verification.sb_4__0_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_5.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_5.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1779,8 +1779,8 @@ initial begin
|
|||
force U0_formal_verification.sb_4__0_.mem_left_track_13.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_15.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_15.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_17.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_17.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_17.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__1_.mem_top_track_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_4__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_4__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -2055,8 +2055,8 @@ initial begin
|
|||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_out[0:2] = 3'b001;
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_outb[0:2] = 3'b110;
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_3.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_4.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
@ -2067,10 +2067,10 @@ initial begin
|
|||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_out[0:2] = 3'b010;
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_outb[0:2] = 3'b101;
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_out[0:2] = 3'b011;
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_outb[0:2] = 3'b100;
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_3__0_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
@ -2393,10 +2393,10 @@ initial begin
|
|||
force U0_formal_verification.cby_2__4_.mem_right_ipin_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cby_2__4_.mem_right_ipin_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cby_2__4_.mem_right_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cby_3__1_.mem_left_ipin_0.mem_out[0:2] = 3'b001;
|
||||
force U0_formal_verification.cby_3__1_.mem_left_ipin_0.mem_outb[0:2] = 3'b110;
|
||||
force U0_formal_verification.cby_3__1_.mem_left_ipin_1.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cby_3__1_.mem_left_ipin_1.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cby_3__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_3__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_3__1_.mem_left_ipin_1.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cby_3__1_.mem_left_ipin_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cby_3__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_3__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_3__1_.mem_right_ipin_1.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -2433,8 +2433,8 @@ initial begin
|
|||
force U0_formal_verification.cby_3__4_.mem_right_ipin_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cby_3__4_.mem_right_ipin_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cby_3__4_.mem_right_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cby_4__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_4__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_4__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_4__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_4__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_4__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_4__1_.mem_left_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
|
|||
|
|
@ -213,7 +213,10 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -222,6 +225,10 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -270,6 +277,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -280,9 +288,13 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2099,6 +2111,15 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2590,8 +2611,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2602,7 +2621,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2654,7 +2672,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2665,13 +2682,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2754,9 +2767,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2789,7 +2799,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2801,7 +2810,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2823,8 +2831,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2968,9 +2974,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3034,11 +3037,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3625,8 +3625,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
|
|
@ -3805,7 +3805,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3908,21 +3908,16 @@
|
|||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3939,6 +3934,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3948,9 +3944,11 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3973,6 +3971,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -4178,7 +4178,7 @@
|
|||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
|
|
|
|||
|
|
@ -430,13 +430,13 @@
|
|||
</bit>
|
||||
<bit id="3998" value="0" path="fpga_top.sb_1__3_.mem_top_track_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3997" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
|
||||
<bit id="3997" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3996" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3995" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]">
|
||||
<bit id="3995" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3994" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
|
||||
<bit id="3994" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3993" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -454,13 +454,13 @@
|
|||
</bit>
|
||||
<bit id="3986" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3985" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
|
||||
<bit id="3985" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3984" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
<bit id="3984" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3983" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
|
||||
<bit id="3983" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3982" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
|
||||
<bit id="3982" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3981" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -558,7 +558,7 @@
|
|||
</bit>
|
||||
<bit id="3934" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3933" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
<bit id="3933" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3932" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -580,19 +580,19 @@
|
|||
</bit>
|
||||
<bit id="3923" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="3922" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
|
||||
<bit id="3922" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="3921" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="3920" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
|
||||
<bit id="3920" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="3919" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3918" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
|
||||
<bit id="3918" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3917" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3916" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
|
||||
<bit id="3916" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3915" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -4226,11 +4226,11 @@
|
|||
</bit>
|
||||
<bit id="2100" value="0" path="fpga_top.sb_2__1_.mem_left_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="2099" value="0" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[3]">
|
||||
<bit id="2099" value="1" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="2098" value="0" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[2]">
|
||||
<bit id="2098" value="1" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="2097" value="0" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[1]">
|
||||
<bit id="2097" value="1" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="2096" value="0" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -5184,9 +5184,9 @@
|
|||
</bit>
|
||||
<bit id="1621" value="0" path="fpga_top.sb_4__1_.mem_top_track_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1620" value="1" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
|
||||
<bit id="1620" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1619" value="1" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[2]">
|
||||
<bit id="1619" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1618" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -5208,7 +5208,7 @@
|
|||
</bit>
|
||||
<bit id="1609" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1608" value="1" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
|
||||
<bit id="1608" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1607" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -5312,7 +5312,7 @@
|
|||
</bit>
|
||||
<bit id="1557" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1556" value="1" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
<bit id="1556" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1555" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -5334,19 +5334,19 @@
|
|||
</bit>
|
||||
<bit id="1546" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="1545" value="1" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
|
||||
<bit id="1545" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="1544" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1543" value="1" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
|
||||
<bit id="1543" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="1542" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1541" value="1" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
|
||||
<bit id="1541" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1540" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1539" value="1" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
|
||||
<bit id="1539" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1538" value="0" path="fpga_top.grid_clb_4__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -5512,11 +5512,11 @@
|
|||
</bit>
|
||||
<bit id="1457" value="0" path="fpga_top.cby_4__1_.mem_left_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1456" value="1" path="fpga_top.cby_4__1_.mem_left_ipin_0.mem_out[2]">
|
||||
<bit id="1456" value="0" path="fpga_top.cby_4__1_.mem_left_ipin_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1455" value="1" path="fpga_top.cby_4__1_.mem_left_ipin_0.mem_out[1]">
|
||||
<bit id="1455" value="0" path="fpga_top.cby_4__1_.mem_left_ipin_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1454" value="1" path="fpga_top.cby_4__1_.mem_left_ipin_0.mem_out[0]">
|
||||
<bit id="1454" value="0" path="fpga_top.cby_4__1_.mem_left_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1453" value="0" path="fpga_top.cbx_4__0_.mem_top_ipin_7.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -5582,7 +5582,7 @@
|
|||
</bit>
|
||||
<bit id="1422" value="0" path="fpga_top.cbx_4__0_.mem_bottom_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1421" value="1" path="fpga_top.sb_4__0_.mem_left_track_17.mem_out[1]">
|
||||
<bit id="1421" value="0" path="fpga_top.sb_4__0_.mem_left_track_17.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1420" value="0" path="fpga_top.sb_4__0_.mem_left_track_17.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -5606,7 +5606,7 @@
|
|||
</bit>
|
||||
<bit id="1410" value="0" path="fpga_top.sb_4__0_.mem_left_track_7.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1409" value="1" path="fpga_top.sb_4__0_.mem_left_track_5.mem_out[1]">
|
||||
<bit id="1409" value="0" path="fpga_top.sb_4__0_.mem_left_track_5.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1408" value="0" path="fpga_top.sb_4__0_.mem_left_track_5.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -5650,9 +5650,9 @@
|
|||
</bit>
|
||||
<bit id="1388" value="0" path="fpga_top.sb_4__0_.mem_top_track_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1387" value="1" path="fpga_top.sb_4__0_.mem_top_track_0.mem_out[1]">
|
||||
<bit id="1387" value="0" path="fpga_top.sb_4__0_.mem_top_track_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1386" value="1" path="fpga_top.sb_4__0_.mem_top_track_0.mem_out[0]">
|
||||
<bit id="1386" value="0" path="fpga_top.sb_4__0_.mem_top_track_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1385" value="0" path="fpga_top.grid_clb_3__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -5940,11 +5940,11 @@
|
|||
</bit>
|
||||
<bit id="1243" value="0" path="fpga_top.cby_3__1_.mem_right_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1242" value="1" path="fpga_top.cby_3__1_.mem_left_ipin_1.mem_out[1]">
|
||||
<bit id="1242" value="0" path="fpga_top.cby_3__1_.mem_left_ipin_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1241" value="1" path="fpga_top.cby_3__1_.mem_left_ipin_1.mem_out[0]">
|
||||
<bit id="1241" value="0" path="fpga_top.cby_3__1_.mem_left_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1240" value="1" path="fpga_top.cby_3__1_.mem_left_ipin_0.mem_out[2]">
|
||||
<bit id="1240" value="0" path="fpga_top.cby_3__1_.mem_left_ipin_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1239" value="0" path="fpga_top.cby_3__1_.mem_left_ipin_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -6072,15 +6072,15 @@
|
|||
</bit>
|
||||
<bit id="1177" value="0" path="fpga_top.sb_3__0_.mem_top_track_16.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1176" value="1" path="fpga_top.sb_3__0_.mem_top_track_10.mem_out[1]">
|
||||
<bit id="1176" value="0" path="fpga_top.sb_3__0_.mem_top_track_10.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1175" value="1" path="fpga_top.sb_3__0_.mem_top_track_10.mem_out[0]">
|
||||
<bit id="1175" value="0" path="fpga_top.sb_3__0_.mem_top_track_10.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1174" value="0" path="fpga_top.sb_3__0_.mem_top_track_8.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1173" value="0" path="fpga_top.sb_3__0_.mem_top_track_8.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1172" value="1" path="fpga_top.sb_3__0_.mem_top_track_2.mem_out[1]">
|
||||
<bit id="1172" value="0" path="fpga_top.sb_3__0_.mem_top_track_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1171" value="0" path="fpga_top.sb_3__0_.mem_top_track_2.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -7254,9 +7254,9 @@
|
|||
</bit>
|
||||
<bit id="586" value="0" path="fpga_top.sb_0__1_.mem_top_track_8.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="585" value="0" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[3]">
|
||||
<bit id="585" value="1" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="584" value="0" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[2]">
|
||||
<bit id="584" value="1" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="583" value="0" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7614,7 +7614,7 @@
|
|||
</bit>
|
||||
<bit id="406" value="0" path="fpga_top.sb_0__4_.mem_right_track_14.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="405" value="0" path="fpga_top.sb_0__4_.mem_right_track_12.mem_out[1]">
|
||||
<bit id="405" value="1" path="fpga_top.sb_0__4_.mem_right_track_12.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="404" value="0" path="fpga_top.sb_0__4_.mem_right_track_12.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -7820,7 +7820,7 @@
|
|||
</bit>
|
||||
<bit id="303" value="1" path="fpga_top.grid_io_top_2__5_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="302" value="1" path="fpga_top.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
<bit id="302" value="0" path="fpga_top.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="301" value="1" path="fpga_top.grid_io_top_2__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -7830,15 +7830,15 @@
|
|||
</bit>
|
||||
<bit id="298" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="297" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[2]">
|
||||
<bit id="297" value="1" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="296" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[1]">
|
||||
<bit id="296" value="1" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="295" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="294" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="293" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_0.mem_out[1]">
|
||||
<bit id="293" value="1" path="fpga_top.cbx_2__4_.mem_top_ipin_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="292" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -7872,7 +7872,7 @@
|
|||
</bit>
|
||||
<bit id="277" value="0" path="fpga_top.cbx_2__4_.mem_bottom_ipin_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="276" value="0" path="fpga_top.cbx_2__4_.mem_bottom_ipin_2.mem_out[2]">
|
||||
<bit id="276" value="1" path="fpga_top.cbx_2__4_.mem_bottom_ipin_2.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="275" value="0" path="fpga_top.cbx_2__4_.mem_bottom_ipin_2.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7892,7 +7892,7 @@
|
|||
</bit>
|
||||
<bit id="267" value="0" path="fpga_top.sb_2__4_.mem_left_track_17.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="266" value="0" path="fpga_top.sb_2__4_.mem_left_track_17.mem_out[2]">
|
||||
<bit id="266" value="1" path="fpga_top.sb_2__4_.mem_left_track_17.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="265" value="0" path="fpga_top.sb_2__4_.mem_left_track_17.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7900,7 +7900,7 @@
|
|||
</bit>
|
||||
<bit id="263" value="0" path="fpga_top.sb_2__4_.mem_left_track_9.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="262" value="0" path="fpga_top.sb_2__4_.mem_left_track_9.mem_out[2]">
|
||||
<bit id="262" value="1" path="fpga_top.sb_2__4_.mem_left_track_9.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="261" value="0" path="fpga_top.sb_2__4_.mem_left_track_9.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7946,9 +7946,9 @@
|
|||
</bit>
|
||||
<bit id="240" value="0" path="fpga_top.sb_2__4_.mem_bottom_track_5.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="239" value="0" path="fpga_top.sb_2__4_.mem_bottom_track_3.mem_out[1]">
|
||||
<bit id="239" value="1" path="fpga_top.sb_2__4_.mem_bottom_track_3.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="238" value="0" path="fpga_top.sb_2__4_.mem_bottom_track_3.mem_out[0]">
|
||||
<bit id="238" value="1" path="fpga_top.sb_2__4_.mem_bottom_track_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="237" value="0" path="fpga_top.sb_2__4_.mem_bottom_track_1.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -8360,7 +8360,7 @@
|
|||
</bit>
|
||||
<bit id="33" value="1" path="fpga_top.grid_io_right_5__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="32" value="0" path="fpga_top.grid_io_right_5__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
<bit id="32" value="1" path="fpga_top.grid_io_right_5__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="31" value="1" path="fpga_top.grid_io_bottom_4__0_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -14,7 +14,7 @@ set_units -time s
|
|||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 9.07571962e-10 -waveform {0 4.53785981e-10} [get_ports {clk[0]}]
|
||||
create_clock -name clk[0] -period 1.084572876e-09 -waveform {0 5.42286438e-10} [get_ports {clk[0]}]
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
-->
|
||||
|
||||
<io_mapping>
|
||||
<io name="gfpga_pad_GPIO_PAD[65:65]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[71:71]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[56:56]" net="c" dir="output"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[13:13]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[12:12]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[10:10]" net="c" dir="output"/>
|
||||
</io_mapping>
|
||||
|
|
|
|||
|
|
@ -30,22 +30,22 @@ set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/ch
|
|||
set_max_delay -from fpga_top/sb_0__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
|
|
|
|||
|
|
@ -38,50 +38,50 @@ set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/ch
|
|||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
|
|
|
|||
|
|
@ -30,22 +30,22 @@ set_max_delay -from fpga_top/sb_0__4_/chany_bottom_in[1] -to fpga_top/sb_0__4_/c
|
|||
set_max_delay -from fpga_top/sb_0__4_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_0__4_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chany_bottom_in[0] -to fpga_top/sb_0__4_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chany_bottom_in[9] -to fpga_top/sb_0__4_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[8] -to fpga_top/sb_0__4_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_0__4_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[7] -to fpga_top/sb_0__4_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[8] -to fpga_top/sb_0__4_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__4_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[6] -to fpga_top/sb_0__4_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[7] -to fpga_top/sb_0__4_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__4_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[5] -to fpga_top/sb_0__4_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[6] -to fpga_top/sb_0__4_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__4_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[4] -to fpga_top/sb_0__4_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[5] -to fpga_top/sb_0__4_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__4_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[3] -to fpga_top/sb_0__4_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[4] -to fpga_top/sb_0__4_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__4_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[2] -to fpga_top/sb_0__4_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[3] -to fpga_top/sb_0__4_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__4_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[1] -to fpga_top/sb_0__4_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[2] -to fpga_top/sb_0__4_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__4_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[0] -to fpga_top/sb_0__4_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[1] -to fpga_top/sb_0__4_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__4_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[0] -to fpga_top/sb_0__4_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_0__4_/chanx_right_in[9] -to fpga_top/sb_0__4_/chany_bottom_out[9] 6.020400151e-11
|
||||
|
|
|
|||
|
|
@ -12,10 +12,10 @@
|
|||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
|
|
@ -23,65 +23,65 @@ set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/ch
|
|||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
|
|
|
|||
|
|
@ -12,118 +12,118 @@
|
|||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/sb_1__1_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
|
|
|
|||
|
|
@ -14,41 +14,41 @@ set_units -time s
|
|||
set_max_delay -from fpga_top/sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[1] -to fpga_top/sb_1__4_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[4] -to fpga_top/sb_1__4_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[7] -to fpga_top/sb_1__4_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[0] -to fpga_top/sb_1__4_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[4] -to fpga_top/sb_1__4_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[8] -to fpga_top/sb_1__4_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[7] -to fpga_top/sb_1__4_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[1] -to fpga_top/sb_1__4_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[4] -to fpga_top/sb_1__4_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[0] -to fpga_top/sb_1__4_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[1] -to fpga_top/sb_1__4_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[5] -to fpga_top/sb_1__4_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[3] -to fpga_top/sb_1__4_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[6] -to fpga_top/sb_1__4_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[9] -to fpga_top/sb_1__4_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[1] -to fpga_top/sb_1__4_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[5] -to fpga_top/sb_1__4_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[0] -to fpga_top/sb_1__4_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_1__4_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_1__4_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[2] -to fpga_top/sb_1__4_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[6] -to fpga_top/sb_1__4_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[2] -to fpga_top/sb_1__4_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[5] -to fpga_top/sb_1__4_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[8] -to fpga_top/sb_1__4_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[2] -to fpga_top/sb_1__4_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[6] -to fpga_top/sb_1__4_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_1__4_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[1] -to fpga_top/sb_1__4_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[7] -to fpga_top/sb_1__4_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_1__4_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[2] -to fpga_top/sb_1__4_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[9] -to fpga_top/sb_1__4_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[8] -to fpga_top/sb_1__4_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[4] -to fpga_top/sb_1__4_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[6] -to fpga_top/sb_1__4_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[8] -to fpga_top/sb_1__4_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[5] -to fpga_top/sb_1__4_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[5] -to fpga_top/sb_1__4_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[6] -to fpga_top/sb_1__4_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[6] -to fpga_top/sb_1__4_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[5] -to fpga_top/sb_1__4_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[4] -to fpga_top/sb_1__4_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[8] -to fpga_top/sb_1__4_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[2] -to fpga_top/sb_1__4_/chany_bottom_out[6] 6.020400151e-11
|
||||
|
|
@ -59,29 +59,29 @@ set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[0] -to fpga_top/sb_1__4_/ch
|
|||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[3] -to fpga_top/sb_1__4_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[0] -to fpga_top/sb_1__4_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_left_in[3] -to fpga_top/sb_1__4_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[0] -to fpga_top/sb_1__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[4] -to fpga_top/sb_1__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[8] -to fpga_top/sb_1__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[2] -to fpga_top/sb_1__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[5] -to fpga_top/sb_1__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[8] -to fpga_top/sb_1__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[1] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[5] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[0] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[3] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[6] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[9] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[2] -to fpga_top/sb_1__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[6] -to fpga_top/sb_1__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[1] -to fpga_top/sb_1__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[4] -to fpga_top/sb_1__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[7] -to fpga_top/sb_1__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[1] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[5] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[3] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[6] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[9] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[0] -to fpga_top/sb_1__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_1__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_1__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[2] -to fpga_top/sb_1__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chanx_right_in[6] -to fpga_top/sb_1__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[7] -to fpga_top/sb_1__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[1] -to fpga_top/sb_1__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_1__4_/chany_bottom_in[4] -to fpga_top/sb_1__4_/chanx_left_out[8] 6.020400151e-11
|
||||
|
|
|
|||
|
|
@ -30,22 +30,22 @@ set_max_delay -from fpga_top/sb_4__0_/chanx_left_in[3] -to fpga_top/sb_4__0_/cha
|
|||
set_max_delay -from fpga_top/sb_4__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_4__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chanx_left_in[2] -to fpga_top/sb_4__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chanx_left_in[1] -to fpga_top/sb_4__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[0] -to fpga_top/sb_4__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_4__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[9] -to fpga_top/sb_4__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[0] -to fpga_top/sb_4__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_4__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[8] -to fpga_top/sb_4__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[9] -to fpga_top/sb_4__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_4__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[7] -to fpga_top/sb_4__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[8] -to fpga_top/sb_4__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_4__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[6] -to fpga_top/sb_4__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[7] -to fpga_top/sb_4__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_4__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[5] -to fpga_top/sb_4__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[6] -to fpga_top/sb_4__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_4__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[4] -to fpga_top/sb_4__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[5] -to fpga_top/sb_4__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_4__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[3] -to fpga_top/sb_4__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[4] -to fpga_top/sb_4__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_4__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[2] -to fpga_top/sb_4__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[3] -to fpga_top/sb_4__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_4__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[2] -to fpga_top/sb_4__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__0_/chany_top_in[1] -to fpga_top/sb_4__0_/chanx_left_out[9] 6.020400151e-11
|
||||
|
|
|
|||
|
|
@ -14,71 +14,71 @@ set_units -time s
|
|||
set_max_delay -from fpga_top/sb_4__1_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_4__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[0] -to fpga_top/sb_4__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[4] -to fpga_top/sb_4__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[8] -to fpga_top/sb_4__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[0] -to fpga_top/sb_4__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[3] -to fpga_top/sb_4__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[6] -to fpga_top/sb_4__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[9] -to fpga_top/sb_4__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[0] -to fpga_top/sb_4__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[0] -to fpga_top/sb_4__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[4] -to fpga_top/sb_4__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[8] -to fpga_top/sb_4__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[1] -to fpga_top/sb_4__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[5] -to fpga_top/sb_4__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[2] -to fpga_top/sb_4__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[5] -to fpga_top/sb_4__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[8] -to fpga_top/sb_4__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[1] -to fpga_top/sb_4__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[5] -to fpga_top/sb_4__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[2] -to fpga_top/sb_4__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[6] -to fpga_top/sb_4__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[7] -to fpga_top/sb_4__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[1] -to fpga_top/sb_4__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[4] -to fpga_top/sb_4__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[7] -to fpga_top/sb_4__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[0] -to fpga_top/sb_4__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[4] -to fpga_top/sb_4__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[8] -to fpga_top/sb_4__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[2] -to fpga_top/sb_4__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[6] -to fpga_top/sb_4__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[7] -to fpga_top/sb_4__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[1] -to fpga_top/sb_4__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[4] -to fpga_top/sb_4__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[7] -to fpga_top/sb_4__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[1] -to fpga_top/sb_4__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[5] -to fpga_top/sb_4__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[0] -to fpga_top/sb_4__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[4] -to fpga_top/sb_4__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[8] -to fpga_top/sb_4__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[2] -to fpga_top/sb_4__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[5] -to fpga_top/sb_4__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[8] -to fpga_top/sb_4__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[2] -to fpga_top/sb_4__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[6] -to fpga_top/sb_4__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[1] -to fpga_top/sb_4__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[5] -to fpga_top/sb_4__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_4__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_4__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_4__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[0] -to fpga_top/sb_4__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[3] -to fpga_top/sb_4__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[6] -to fpga_top/sb_4__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[9] -to fpga_top/sb_4__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chanx_left_in[0] -to fpga_top/sb_4__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[2] -to fpga_top/sb_4__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[6] -to fpga_top/sb_4__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_4__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[0] -to fpga_top/sb_4__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[3] -to fpga_top/sb_4__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_4__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_4__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[0] -to fpga_top/sb_4__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[3] -to fpga_top/sb_4__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_4__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[1] -to fpga_top/sb_4__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[7] -to fpga_top/sb_4__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[2] -to fpga_top/sb_4__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[9] -to fpga_top/sb_4__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[8] -to fpga_top/sb_4__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[4] -to fpga_top/sb_4__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[6] -to fpga_top/sb_4__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[8] -to fpga_top/sb_4__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[5] -to fpga_top/sb_4__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[5] -to fpga_top/sb_4__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[6] -to fpga_top/sb_4__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[6] -to fpga_top/sb_4__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[5] -to fpga_top/sb_4__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[4] -to fpga_top/sb_4__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_bottom_in[8] -to fpga_top/sb_4__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__1_/chany_top_in[2] -to fpga_top/sb_4__1_/chanx_left_out[8] 6.020400151e-11
|
||||
|
|
|
|||
|
|
@ -30,22 +30,22 @@ set_max_delay -from fpga_top/sb_4__4_/chanx_left_in[8] -to fpga_top/sb_4__4_/cha
|
|||
set_max_delay -from fpga_top/sb_4__4_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_4__4_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chanx_left_in[9] -to fpga_top/sb_4__4_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chanx_left_in[0] -to fpga_top/sb_4__4_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[9] -to fpga_top/sb_4__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_4__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[0] -to fpga_top/sb_4__4_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[9] -to fpga_top/sb_4__4_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_4__4_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[1] -to fpga_top/sb_4__4_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[0] -to fpga_top/sb_4__4_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_4__4_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[2] -to fpga_top/sb_4__4_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[1] -to fpga_top/sb_4__4_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_4__4_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[3] -to fpga_top/sb_4__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[2] -to fpga_top/sb_4__4_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_4__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[4] -to fpga_top/sb_4__4_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[3] -to fpga_top/sb_4__4_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_4__4_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[5] -to fpga_top/sb_4__4_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[4] -to fpga_top/sb_4__4_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_4__4_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[6] -to fpga_top/sb_4__4_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[5] -to fpga_top/sb_4__4_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_4__4_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[7] -to fpga_top/sb_4__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[6] -to fpga_top/sb_4__4_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_4__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[7] -to fpga_top/sb_4__4_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_top/sb_4__4_/chany_bottom_in[8] -to fpga_top/sb_4__4_/chanx_left_out[9] 6.020400151e-11
|
||||
|
|
|
|||
Loading…
Reference in New Issue