[test] fixed a few bugs
This commit is contained in:
tangxifan
parent
9bc9b61d35
commit
ce0fbe1765
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@ -1,7 +1,7 @@
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# Use a FF with constant input to connect a clock signal (frequency divided by 2) from a global network to datapath
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# Use an external signal to enable the clock signal
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.model clk_gate
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.inputs clk_i data_i
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.inputs rst_i clk_i data_i
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.outputs data_o
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.names $true
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@ -13,6 +13,6 @@
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.names ff_o data_i data_o
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11 1
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.latch ff_i ff_o re clk_i 0
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.subckt dffr D=ff_i Q=ff_o C=clk_i R=rst_i
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.end
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@ -6,17 +6,22 @@
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`timescale 1ns / 1ps
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module clk_gate(
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rst_i,
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clk_i,
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data_i,
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data_o);
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input wire rst_i;
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input wire clk_i;
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input wire data_i;
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output wire data_o;
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reg q;
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always @(posedge clk_i) begin
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q <= 1;
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if (rst_i) begin
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q <= 0;
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end else begin
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q <= 1;
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end
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end
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assign data_o = data_i & q;
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@ -0,0 +1,76 @@
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# Run VPR for the 'and' design
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --skip_sync_clustering_and_routing_results on --absorb_buffer_luts off
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --sort_gsb_chan_node_in_edges
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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# Apply fix-up to clustering nets based on routing results
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pb_pin_fixup --verbose
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# Apply fix-up to Look-Up Table truth tables based on packing results
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lut_truth_table_fixup
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing #--verbose
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# Write the fabric hierarchy of module graph to a file
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# This is used by hierarchical PnR flows
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write_fabric_hierarchy --file ./fabric_hierarchy.txt
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# Repack the netlist to physical pbs
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# This must be done before bitstream generator and testbench generation
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# Strongly recommend it is done after all the fix-up have been applied
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repack #--verbose
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# Build the bitstream
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# - Output the fabric-independent bitstream to a file
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build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
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# Build fabric-dependent bitstream
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build_fabric_bitstream --verbose
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# Write fabric-dependent bitstream
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write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
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# Write the Verilog netlist for FPGA fabric
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# - Enable the use of explicit port mapping in Verilog netlist
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write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
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# Write the Verilog testbench for FPGA fabric
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# - We suggest the use of same output directory as fabric Verilog netlists
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# - Must specify the reference benchmark file if you want to output any testbenches
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# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
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# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
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# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
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write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit
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write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
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write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
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# Write the SDC files for PnR backend
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# - Turn on every options here
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write_pnr_sdc --file ./SDC
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# Write SDC to disable timing for configure ports
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write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
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# Write the SDC to run timing analysis for a mapped FPGA fabric
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write_analysis_sdc --file ./SDC_analysis
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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@ -25,6 +25,7 @@ run-task fpga_bitstream/load_external_architecture_bitstream $@
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echo -e "Testing repacker capability in identifying wire LUTs";
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run-task fpga_bitstream/repack_wire_lut $@
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run-task fpga_bitstream/repack_wire_lut_strong $@
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echo -e "Testing overloading default paths for programmable interconnect when generating bitstream";
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run-task fpga_bitstream/overload_mux_default_path $@
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@ -1,4 +0,0 @@
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<!-- A dummy pin constraint file, useful when no pin constraints are needed for a benchmark -->
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<pin_constraints>
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</pin_constraints>
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@ -16,13 +16,13 @@ timeout_each_job = 20*60
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fpga_flow=vpr_blif
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/wire_lut_example_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
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openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_dummy.xml
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openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints.xml
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N1_tileable_40nm.xml
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N1_tileable_fracff_40nm.xml
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[BENCHMARKS]
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#
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@ -7,11 +7,7 @@
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with optionally registered outputs
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- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
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Details on Modelling:
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Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
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Authors: Jason Luu, Jeff Goeders, Vaughn Betz
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Authors: Xifan Tang
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--><architecture>
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<!--
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ODIN II specific config begins
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@ -42,6 +38,38 @@
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<port name="lut4_out"/>
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</output_ports>
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</model>
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<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
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<model name="dff">
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<input_ports>
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<port name="D" clock="C"/>
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<port name="C" is_clock="1"/>
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</input_ports>
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<output_ports>
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<port name="Q" clock="C"/>
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</output_ports>
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</model>
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<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
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<model name="dffr">
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<input_ports>
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<port name="D" clock="C"/>
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<port name="R" clock="C"/>
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<port name="C" is_clock="1"/>
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</input_ports>
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<output_ports>
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<port name="Q" clock="C"/>
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</output_ports>
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</model>
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<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
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<model name="dffrn">
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<input_ports>
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<port name="D" clock="C"/>
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<port name="RN" clock="C"/>
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<port name="C" is_clock="1"/>
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</input_ports>
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<output_ports>
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<port name="Q" clock="C"/>
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</output_ports>
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</model>
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</models>
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<tiles>
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<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
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@ -67,9 +95,13 @@
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<site pb_type="clb"/>
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</equivalent_sites>
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<input name="I" num_pins="4" equivalent="full"/>
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<input name="reset" num_pins="1" is_non_clock_global="true"/>
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<output name="O" num_pins="2" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
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<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
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<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
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</fc>
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<pinlocations pattern="spread"/>
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</sub_tile> </tile>
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</tiles>
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@ -97,6 +129,13 @@
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</fixed_layout>
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<fixed_layout name="48x48" width="50" height="50">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</fixed_layout>
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</layout>
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<device>
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<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
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@ -230,6 +269,7 @@
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-->
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<pb_type name="clb">
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<input name="I" num_pins="4" equivalent="full"/>
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<input name="reset" num_pins="1"/>
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<output name="O" num_pins="2" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<!-- Describe fracturable logic element.
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@ -238,12 +278,14 @@
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-->
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<pb_type name="fle" num_pb="1">
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<input name="in" num_pins="4"/>
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<input name="reset" num_pins="1"/>
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<output name="out" num_pins="2"/>
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<clock name="clk" num_pins="1"/>
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<!-- Physical mode definition begin (physical implementation of the fle) -->
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<mode name="physical" disable_packing="true">
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<pb_type name="fabric" num_pb="1">
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<input name="in" num_pins="4"/>
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<input name="reset" num_pins="1"/>
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<output name="out" num_pins="2"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="frac_logic" num_pb="1">
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@ -263,17 +305,20 @@
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</interconnect>
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</pb_type>
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<!-- Define flip-flop -->
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<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
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<pb_type name="ff" blif_model=".subckt dffr" num_pb="2">
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<input name="D" num_pins="1" port_class="D"/>
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<input name="R" num_pins="1"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="C"/>
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<T_setup value="66e-12" port="ff.R" clock="C"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="C"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
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<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
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<complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
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<complete name="direct3" input="fabric.clk" output="ff[1:0].C"/>
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<complete name="direct4" input="fabric.reset" output="ff[1:0].R"/>
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<mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
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@ -290,6 +335,7 @@
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<direct name="direct1" input="fle.in" output="fabric.in"/>
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<direct name="direct2" input="fabric.out" output="fle.out"/>
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<direct name="direct3" input="fle.clk" output="fabric.clk"/>
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<direct name="direct4" input="fle.reset" output="fabric.reset"/>
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</interconnect>
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</mode>
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<!-- Physical mode definition end (physical implementation of the fle) -->
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@ -297,10 +343,12 @@
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<mode name="n2_lut3">
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<pb_type name="lut3inter" num_pb="1">
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<input name="in" num_pins="3"/>
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<input name="reset" num_pins="1"/>
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<output name="out" num_pins="2"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="ble3" num_pb="2">
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<input name="in" num_pins="3"/>
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<input name="reset" num_pins="1"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- Define the LUT -->
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@ -323,20 +371,82 @@
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</delay_matrix>
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</pb_type>
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<!-- Define the flip-flop -->
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<pb_type name="ff" num_pb="1">
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<input name="D" num_pins="1"/>
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<input name="R" num_pins="1"/>
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<output name="Q" num_pins="1"/>
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<clock name="C" num_pins="1"/>
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<mode name="latch">
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<pb_type name="latch" blif_model=".latch" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="latch.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="latch.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ff.D" output="latch.D"/>
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<direct name="direct2" input="ff.C" output="latch.clk"/>
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<direct name="direct3" input="latch.Q" output="ff.Q"/>
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</interconnect>
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</mode>
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<mode name="dff">
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<pb_type name="dff" blif_model=".subckt dff" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="dff.D" clock="C"/>
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<T_clock_to_Q max="124e-12" port="dff.Q" clock="C"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ff.D" output="dff.D"/>
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<direct name="direct2" input="ff.C" output="dff.C"/>
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<direct name="direct3" input="dff.Q" output="ff.Q"/>
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</interconnect>
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</mode>
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<mode name="dffr">
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<pb_type name="dffr" blif_model=".subckt dffr" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<input name="R" num_pins="1"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="dffr.D" clock="C"/>
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<T_setup value="66e-12" port="dffr.R" clock="C"/>
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<T_clock_to_Q max="124e-12" port="dffr.Q" clock="C"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ff.D" output="dffr.D"/>
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<direct name="direct2" input="ff.C" output="dffr.C"/>
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<direct name="direct3" input="ff.R" output="dffr.R"/>
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<direct name="direct4" input="dffr.Q" output="ff.Q"/>
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</interconnect>
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</mode>
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<mode name="dffrn">
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<pb_type name="dffrn" blif_model=".subckt dffrn" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<input name="RN" num_pins="1"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="dffrn.D" clock="C"/>
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<T_setup value="66e-12" port="dffrn.RN" clock="C"/>
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<T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ff.D" output="dffrn.D"/>
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<direct name="direct2" input="ff.C" output="dffrn.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffrn.RN"/>
|
||||
<direct name="direct4" input="dffrn.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
|
||||
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
|
||||
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
|
||||
<direct name="direct3" input="ble3.clk" output="ff[0:0].C"/>
|
||||
<direct name="direct4" input="ble3.reset" output="ff[0:0].R"/>
|
||||
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
|
||||
|
|
@ -349,12 +459,14 @@
|
|||
<direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
|
||||
<direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
|
||||
<complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
|
||||
<complete name="complete2" input="lut3inter.reset" output="ble3[1:0].reset"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
|
||||
<direct name="direct2" input="lut3inter.out" output="fle.out"/>
|
||||
<direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
|
||||
<direct name="direct4" input="fle.reset" output="lut3inter.reset"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Dual 3-LUT mode definition end -->
|
||||
|
|
@ -363,6 +475,7 @@
|
|||
<!-- Define 4-LUT mode -->
|
||||
<pb_type name="ble4" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Define LUT -->
|
||||
|
|
@ -386,21 +499,83 @@
|
|||
261e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<!-- Define flip-flop -->
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<!-- Define the flip-flop -->
|
||||
<pb_type name="ff" num_pb="1">
|
||||
<input name="D" num_pins="1"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1"/>
|
||||
<clock name="C" num_pins="1"/>
|
||||
<mode name="latch">
|
||||
<pb_type name="latch" blif_model=".latch" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="latch.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="latch.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="latch.D"/>
|
||||
<direct name="direct2" input="ff.C" output="latch.clk"/>
|
||||
<direct name="direct3" input="latch.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dff">
|
||||
<pb_type name="dff" blif_model=".subckt dff" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dff.D" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dff.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dff.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dff.C"/>
|
||||
<direct name="direct3" input="dff.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffr">
|
||||
<pb_type name="dffr" blif_model=".subckt dffr" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffr.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffr.R" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffr.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffr.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffr.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffr.R"/>
|
||||
<direct name="direct4" input="dffr.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffrn">
|
||||
<pb_type name="dffrn" blif_model=".subckt dffrn" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="RN" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffrn.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffrn.RN" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffrn.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffrn.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffrn.RN"/>
|
||||
<direct name="direct4" input="dffrn.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
|
||||
<direct name="direct2" input="lut4.out" output="ff.D">
|
||||
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
|
||||
<direct name="direct3" input="ble4.clk" output="ff.C"/>
|
||||
<direct name="direct4" input="ble4.reset" output="ff.R"/>
|
||||
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
|
||||
|
|
@ -412,6 +587,7 @@
|
|||
<direct name="direct1" input="fle.in" output="ble4.in"/>
|
||||
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
|
||||
<direct name="direct4" input="fle.reset" output="ble4.reset"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- 6-LUT mode definition end -->
|
||||
|
|
@ -431,6 +607,8 @@
|
|||
<delay_constant max="75e-12" in_port="fle[0:0].out" out_port="fle[0:0].in"/>
|
||||
</complete>
|
||||
<complete name="clks" input="clb.clk" output="fle[0:0].clk">
|
||||
</complete>
|
||||
<complete name="resets" input="clb.reset" output="fle[0:0].reset">
|
||||
</complete>
|
||||
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
|
||||
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
|
||||
Loading…
Reference in New Issue