From ce0fbe1765b49078de239d90a178f16f740b2e90 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 29 Sep 2022 15:32:31 -0700 Subject: [PATCH] [test] fixed a few bugs --- .../micro_benchmark/clk_gate/clk_gate.blif | 4 +- .../micro_benchmark/clk_gate/clk_gate.v | 9 +- .../wire_lut_example_script.openfpga | 76 ++++++ .../fpga_bitstream_reg_test.sh | 1 + .../config/pin_constraints_dummy.xml | 4 - .../repack_wire_lut_strong/config/task.conf | 8 +- ...ml => k4_frac_N1_tileable_fracff_40nm.xml} | 234 +++++++++++++++--- 7 files changed, 296 insertions(+), 40 deletions(-) create mode 100644 openfpga_flow/openfpga_shell_scripts/wire_lut_example_script.openfpga delete mode 100644 openfpga_flow/tasks/fpga_bitstream/repack_wire_lut_strong/config/pin_constraints_dummy.xml rename openfpga_flow/vpr_arch/{k4_frac_N1_tileable_40nm.xml => k4_frac_N1_tileable_fracff_40nm.xml} (65%) diff --git a/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.blif b/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.blif index 30cb43bec..e867a9796 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.blif +++ b/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.blif @@ -1,7 +1,7 @@ # Use a FF with constant input to connect a clock signal (frequency divided by 2) from a global network to datapath # Use an external signal to enable the clock signal .model clk_gate -.inputs clk_i data_i +.inputs rst_i clk_i data_i .outputs data_o .names $true @@ -13,6 +13,6 @@ .names ff_o data_i data_o 11 1 -.latch ff_i ff_o re clk_i 0 +.subckt dffr D=ff_i Q=ff_o C=clk_i R=rst_i .end diff --git a/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.v b/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.v index 382fc03a5..99a57c553 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.v +++ b/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.v @@ -6,17 +6,22 @@ `timescale 1ns / 1ps module clk_gate( + rst_i, clk_i, data_i, data_o); - +input wire rst_i; input wire clk_i; input wire data_i; output wire data_o; reg q; always @(posedge clk_i) begin - q <= 1; + if (rst_i) begin + q <= 0; + end else begin + q <= 1; + end end assign data_o = data_i & q; diff --git a/openfpga_flow/openfpga_shell_scripts/wire_lut_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/wire_lut_example_script.openfpga new file mode 100644 index 000000000..b66992eb7 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/wire_lut_example_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --skip_sync_clustering_and_routing_results on --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh index 6ddee3f9f..6df03b3af 100755 --- a/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh @@ -25,6 +25,7 @@ run-task fpga_bitstream/load_external_architecture_bitstream $@ echo -e "Testing repacker capability in identifying wire LUTs"; run-task fpga_bitstream/repack_wire_lut $@ +run-task fpga_bitstream/repack_wire_lut_strong $@ echo -e "Testing overloading default paths for programmable interconnect when generating bitstream"; run-task fpga_bitstream/overload_mux_default_path $@ diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_wire_lut_strong/config/pin_constraints_dummy.xml b/openfpga_flow/tasks/fpga_bitstream/repack_wire_lut_strong/config/pin_constraints_dummy.xml deleted file mode 100644 index 07c78141f..000000000 --- a/openfpga_flow/tasks/fpga_bitstream/repack_wire_lut_strong/config/pin_constraints_dummy.xml +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_wire_lut_strong/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/repack_wire_lut_strong/config/task.conf index 132cfbfc8..0d8268787 100644 --- a/openfpga_flow/tasks/fpga_bitstream/repack_wire_lut_strong/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/repack_wire_lut_strong/config/task.conf @@ -16,13 +16,13 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/wire_lut_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_dummy.xml +openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints.xml [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N1_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N1_tileable_fracff_40nm.xml [BENCHMARKS] # diff --git a/openfpga_flow/vpr_arch/k4_frac_N1_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N1_tileable_fracff_40nm.xml similarity index 65% rename from openfpga_flow/vpr_arch/k4_frac_N1_tileable_40nm.xml rename to openfpga_flow/vpr_arch/k4_frac_N1_tileable_fracff_40nm.xml index dd5cca16d..33b81cf2f 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N1_tileable_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N1_tileable_fracff_40nm.xml @@ -7,11 +7,7 @@ with optionally registered outputs - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1 - Details on Modelling: - - Based on flagship k4_frac_N4_mem32K_40nm.xml architecture. - - Authors: Jason Luu, Jeff Goeders, Vaughn Betz + Authors: Xifan Tang --> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -263,17 +305,20 @@ - + + - - - + + + + - + + @@ -290,6 +335,7 @@ + @@ -297,10 +343,12 @@ + + @@ -323,20 +371,82 @@ - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + @@ -349,12 +459,14 @@ + + @@ -363,6 +475,7 @@ + @@ -386,21 +499,83 @@ 261e-12 - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + @@ -412,6 +587,7 @@ + @@ -431,6 +607,8 @@ + +