[Script] Add an example script to test option ``--no_time_stamp``

openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga

@@ -0,0 +1,83 @@
+# !!! IMPRORTANT
+# This script is designed to test the option --no_time_stamp in related commands
+# It can NOT be used an example script to achieve other objectives
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file ${OPENFPGA_OUTPUT_DIR}/fabric_independent_bitstream.xml --no_time_stamp
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose 
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file ${OPENFPGA_OUTPUT_DIR}/fabric_bitstream.xml --format xml --no_time_stamp
+write_fabric_bitstream --file ${OPENFPGA_OUTPUT_DIR}/fabric_bitstream.bit --format plain_text --no_time_stamp
+write_io_mapping --file ${OPENFPGA_OUTPUT_DIR}/pin_mapping.xml --no_time_stamp
+report_bitstream_distribution --file ${OPENFPGA_OUTPUT_DIR}/bitstream_distribution.xml --no_time_stamp
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --include_timing --print_user_defined_template --verbose --no_time_stamp
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --no_time_stamp
+write_preconfigured_testbench --file ${OPENFPGA_OUTPUT_DIR} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --no_time_stamp
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ${OPENFPGA_OUTPUT_DIR} --no_time_stamp
+
+# Write SDC to constrain timing of configuration chain
+write_configuration_chain_sdc --file ${OPENFPGA_OUTPUT_DIR}/ccff_timing.sdc --time_unit ns --max_delay 5 --min_delay 2.5 --no_time_stamp
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ${OPENFPGA_OUTPUT_DIR}/disable_configure_ports.sdc --no_time_stamp
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ${OPENFPGA_OUTPUT_DIR} --no_time_stamp
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory