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[Arch] Syntax error fix

This commit is contained in:
tangxifan 2022-01-02 20:27:00 -08:00
parent 628191da5f
commit 9c476ed5db
1 changed files with 4 additions and 4 deletions
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8
openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
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@ -380,9 +380,9 @@
</direct>
<direct name="out2out" input="mult_8x8.Y" output="mult_8x8_slice.OUT_cfg">
</direct>
<complete name="clk_ff_A" input="mult_8x8.clk" output="ff_A.clk">
<complete name="clk_ff_B" input="mult_8x8.clk" output="ff_B.clk">
<complete name="clk_ff_Y" input="mult_8x8.clk" output="ff_Y.clk">
<complete name="clk_ff_A" input="mult_8x8.clk" output="ff_A.clk"/>
<complete name="clk_ff_B" input="mult_8x8.clk" output="ff_B.clk"/>
<complete name="clk_ff_Y" input="mult_8x8.clk" output="ff_Y.clk"/>
</interconnect>
<power method="pin-toggle">
<port name="A_cfg" energy_per_toggle="2.13e-12"/>
@ -405,7 +405,7 @@
<direct name="out2out" input="mult_8x8_slice.OUT_cfg" output="mult_8.out">
<delay_constant max="1.93e-9" min="74e-12" in_port="mult_8x8_slice.OUT_cfg" out_port="mult_8.out"/>
</direct>
<complete name="clk" input="mult_8.clk" output="mult_8x8_slice.clk">
<complete name="clk" input="mult_8.clk" output="mult_8x8_slice.clk"/>
</interconnect>
</mode>
<!-- Place this multiplier block every 8 columns from (and including) the sixth column -->