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[Test] Add new test case (DSP with registers) into FPGA-Verilog regression tests

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tangxifan 2022-01-02 20:21:58 -08:00
parent 824a03bdca
commit 628191da5f
1 changed files with 3 additions and 0 deletions
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openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
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@ -53,6 +53,9 @@ run-task fpga_verilog/dsp/multi_mode_mult_16x16 --debug --show_thread_logs
echo -e "Testing Verilog generation with heterogeneous fabric using multi-width 16-bit multi-mode multipliers ";
run-task fpga_verilog/dsp/wide_multi_mode_mult_16x16 --debug --show_thread_logs
echo -e "Testing Verilog generation with heterogeneous fabric using 8-bit single-mode registerable multipliers ";
run-task fpga_verilog/dsp/single_mode_mult_8x8_reg --debug --show_thread_logs
echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
run-task fpga_verilog/io/multi_io_capacity --debug --show_thread_logs