[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work

openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v

@@ -15,6 +15,10 @@ module counter (
 
 	reg [127:0] result;
 
+    initial begin
+      result <= 0;
+    end
+
 	always @(posedge clk or posedge reset)
 	begin
 		if (reset) 

openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v

@@ -15,6 +15,10 @@ module counter (
 
 	reg [127:0] result;
 
+    initial begin
+      result <= 0;
+    end
+
 	always @(posedge clk or negedge resetb)
 	begin
 		if (~resetb) 

openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v

@@ -10,6 +10,11 @@ module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
     output [3:0] q1;
     reg [3:0] q1;
 
+    initial begin
+      q0 <= 0;
+      q1 <= 0;
+    end
+
     always @ (posedge clk0)
     begin
         if(rst0)

openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v

@@ -15,6 +15,10 @@ module counter (
 
 	reg [7:0] result;
 
+    initial begin
+      result <= 0;
+    end
+
 	always @(posedge clk or posedge reset)
 	begin
 		if (reset) 

openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v

@@ -15,6 +15,10 @@ module counter (
 
 	reg [7:0] result;
 
+    initial begin
+      result <= 0;
+    end
+
 	always @(posedge clk or negedge resetb)
 	begin
 		if (!resetb) 

openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v

@@ -5,6 +5,10 @@ module counter(clk_counter, q_counter, rst_counter);
     output [7:0] q_counter;
     reg [7:0] q_counter;
 
+    initial begin
+      q_counter <= 0;
+    end
+
     always @ (posedge clk_counter)
     begin
         if(rst_counter)