From 7121513396c3d90e0ab24a5129b1793041a943fe Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 15 Feb 2022 15:21:08 -0800 Subject: [PATCH] [HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work --- .../counters/counter_128bit_async_reset/counter.v | 4 ++++ .../counters/counter_128bit_async_resetb/counter.v | 4 ++++ .../counters/counter_4bit_2clock/counter_4bit_2clock.v | 5 +++++ .../counters/counter_8bit_async_reset/counter.v | 4 ++++ .../counters/counter_8bit_async_resetb/counter.v | 4 ++++ .../counters/counter_8bit_sync_reset/counter.v | 4 ++++ 6 files changed, 25 insertions(+) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v index 4a3542eec..ead38700f 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v @@ -15,6 +15,10 @@ module counter ( reg [127:0] result; + initial begin + result <= 0; + end + always @(posedge clk or posedge reset) begin if (reset) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v index 628ec4c08..fda46b891 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v @@ -15,6 +15,10 @@ module counter ( reg [127:0] result; + initial begin + result <= 0; + end + always @(posedge clk or negedge resetb) begin if (~resetb) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v index c1b5f2ee6..ae52fbfe6 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v @@ -10,6 +10,11 @@ module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1); output [3:0] q1; reg [3:0] q1; + initial begin + q0 <= 0; + q1 <= 0; + end + always @ (posedge clk0) begin if(rst0) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v index 685b77577..0997e1b63 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v @@ -15,6 +15,10 @@ module counter ( reg [7:0] result; + initial begin + result <= 0; + end + always @(posedge clk or posedge reset) begin if (reset) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v index 3d929091d..3d7869948 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v @@ -15,6 +15,10 @@ module counter ( reg [7:0] result; + initial begin + result <= 0; + end + always @(posedge clk or negedge resetb) begin if (!resetb) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v index 216053285..10f0e1c4b 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v @@ -5,6 +5,10 @@ module counter(clk_counter, q_counter, rst_counter); output [7:0] q_counter; reg [7:0] q_counter; + initial begin + q_counter <= 0; + end + always @ (posedge clk_counter) begin if(rst_counter)