[test] replace hardcoded paths in task config files with relative paths
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@ -21,9 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_vpr_device_layout=4x4
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openfpga_vpr_route_chan_width=20
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openfpga_pcf=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf
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openfpga_io_map_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml
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openfpga_pin_table=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv
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openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
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openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
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openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
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openfpga_vpr_fix_pins_file=and2_fix_pins.place
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[ARCHITECTURES]
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@ -21,9 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_vpr_device_layout=4x4
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openfpga_vpr_route_chan_width=20
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openfpga_pcf=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf
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openfpga_io_map_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml
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openfpga_pin_table=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv
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openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
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openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
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openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
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openfpga_vpr_fix_pins_file=and2_fix_pins.place
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[ARCHITECTURES]
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@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_vpr_device_layout=2x2
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openfpga_vpr_route_chan_width=20
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openfpga_vpr_fix_pins_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/fix_pins/config/and2_fix_pins.place
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openfpga_vpr_fix_pins_file=${PATH:TASK_DIR}/config/and2_fix_pins.place
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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