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Merge branch 'master' into rst_on_lut_strong

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tangxifan 2022-10-13 16:01:57 -07:00 committed by GitHub
parent 33e2b16cb1 07441a978c
commit e9ee039e60
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4 changed files with 20 additions and 16 deletions
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12
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
View File

@ -286,18 +286,18 @@
of the input/output of the 32x32 multiplier
-->
<pb_type name="mult_32[two_divisible_mult_16x16].divisible_mult_16x16[two_mult_8x8].mult_8x8_slice.mult_8x8" physical_pb_type_name="mult_32[mult_32x32].mult_32x32_slice.mult_32x32" mode_bits="01" physical_pb_type_index_factor="0">
<port name="a" physical_mode_port="a[0:7]" physical_mode_pin_rotate_offset="8"/>
<port name="b" physical_mode_port="b[0:7]" physical_mode_pin_rotate_offset="8"/>
<port name="out" physical_mode_port="out[0:15]" physical_mode_pin_rotate_offset="16"/>
<port name="a" physical_mode_port="a[0:7]" physical_mode_port_rotate_offset="8"/>
<port name="b" physical_mode_port="b[0:7]" physical_mode_port_rotate_offset="8"/>
<port name="out" physical_mode_port="out[0:15]" physical_mode_port_rotate_offset="16"/>
</pb_type>
<!-- Bind the 16x16 multiplier to the physical 32x32 multiplier
There are two 16x16 multipliers, each of which occupies part
of the input/output of the 32x32 multiplier
-->
<pb_type name="mult_32[two_divisible_mult_16x16].divisible_mult_16x16[mult_16x16].mult_16x16_slice.mult_16x16" physical_pb_type_name="mult_32[mult_32x32].mult_32x32_slice.mult_32x32" mode_bits="10" physical_pb_type_index_factor="0">
<port name="a" physical_mode_port="a[0:15]" physical_mode_pin_rotate_offset="16"/>
<port name="b" physical_mode_port="b[0:15]" physical_mode_pin_rotate_offset="16"/>
<port name="out" physical_mode_port="out[0:31]" physical_mode_pin_rotate_offset="32"/>
<port name="a" physical_mode_port="a[0:15]" physical_mode_port_rotate_offset="16"/>
<port name="b" physical_mode_port="b[0:15]" physical_mode_port_rotate_offset="16"/>
<port name="out" physical_mode_port="out[0:31]" physical_mode_port_rotate_offset="32"/>
</pb_type>
<!-- END physical pb_type binding in complex block dsp -->
</pb_type_annotations>

12
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
View File

@ -298,18 +298,18 @@
of the input/output of the 36x36 multiplier
-->
<pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[two_mult_9x9].mult_9x9_slice.mult_9x9" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="01" physical_pb_type_index_factor="0">
<port name="a" physical_mode_port="a[0:8]" physical_mode_pin_rotate_offset="9"/>
<port name="b" physical_mode_port="b[0:8]" physical_mode_pin_rotate_offset="9"/>
<port name="out" physical_mode_port="out[0:17]" physical_mode_pin_rotate_offset="18"/>
<port name="a" physical_mode_port="a[0:8]" physical_mode_port_rotate_offset="9"/>
<port name="b" physical_mode_port="b[0:8]" physical_mode_port_rotate_offset="9"/>
<port name="out" physical_mode_port="out[0:17]" physical_mode_port_rotate_offset="18"/>
</pb_type>
<!-- Bind the 18x18 multiplier to the physical 36x36 multiplier
There are two 18x18 multipliers, each of which occupies part
of the input/output of the 36x36 multiplier
-->
<pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[mult_18x18].mult_18x18_slice.mult_18x18" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="10" physical_pb_type_index_factor="0">
<port name="a" physical_mode_port="a[0:17]" physical_mode_pin_rotate_offset="18"/>
<port name="b" physical_mode_port="b[0:17]" physical_mode_pin_rotate_offset="18"/>
<port name="out" physical_mode_port="out[0:35]" physical_mode_pin_rotate_offset="36"/>
<port name="a" physical_mode_port="a[0:17]" physical_mode_port_rotate_offset="18"/>
<port name="b" physical_mode_port="b[0:17]" physical_mode_port_rotate_offset="18"/>
<port name="out" physical_mode_port="out[0:35]" physical_mode_port_rotate_offset="36"/>
</pb_type>
<!-- END physical pb_type binding in complex block dsp -->
<!-- physical pb_type binding in complex block memory -->

10
openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v
View File

@ -161,13 +161,17 @@ module frac_mem_32k (
end else if (4'b0111 == mode) begin
if (we_a) begin
ram_a[addr_a[0:9]] <= data_a;
ram_b[addr_b[0:9]] <= data_b;
q_a <= data_a;
q_b <= data_b;
end else begin
q_a <= ram_a[addr_a[0:9]];
end
if (we_b) begin
ram_b[addr_b[0:9]] <= data_b;
q_b <= data_b;
end else begin
q_b <= ram_b[addr_b[0:9]];
end
end
// Operating mode: dual port RAM 2048 x 16
end else if (4'b1000 == mode) begin
if (we_a) begin

2
yosys-plugins

@ -1 +1 @@
Subproject commit 27208ce08200a5e89e3bd4f466bc68824df38c32
Subproject commit b3430d2e55181ab12ea67396a59c753fd342bbbc