From c45b51a31996d5fd90719ae8fc44036a3f576d58 Mon Sep 17 00:00:00 2001
From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com>
Date: Wed, 12 Oct 2022 06:19:46 +0000
Subject: [PATCH 1/4] Bump yosys-plugins from `27208ce` to `b3430d2`

Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `27208ce` to `b3430d2`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](https://github.com/SymbiFlow/yosys-symbiflow-plugins/compare/27208ce08200a5e89e3bd4f466bc68824df38c32...b3430d2e55181ab12ea67396a59c753fd342bbbc)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
---
 yosys-plugins | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/yosys-plugins b/yosys-plugins
index 27208ce08..b3430d2e5 160000
--- a/yosys-plugins
+++ b/yosys-plugins
@@ -1 +1 @@
-Subproject commit 27208ce08200a5e89e3bd4f466bc68824df38c32
+Subproject commit b3430d2e55181ab12ea67396a59c753fd342bbbc

From f62d435b1ea7c7e568fe0755b40dce6151808ae0 Mon Sep 17 00:00:00 2001
From: Yunus Emre ERYILMAZ <30428379+yunuseryilmaz18@users.noreply.github.com>
Date: Wed, 12 Oct 2022 09:35:35 +0300
Subject: [PATCH 2/4] Update frac_mem_32k.v

---
 .../openfpga_cell_library/verilog/frac_mem_32k.v       | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v b/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v
index 2d0b8fd26..b99753e7f 100644
--- a/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v
@@ -161,13 +161,17 @@ module frac_mem_32k (
     end else if (4'b0111 == mode) begin 
       if (we_a) begin
         ram_a[addr_a[0:9]] <= data_a;
-        ram_b[addr_b[0:9]] <= data_b;
         q_a <= data_a;
-        q_b <= data_b;
       end else begin
         q_a <= ram_a[addr_a[0:9]];
+      end
+      
+      if (we_b) begin
+        ram_b[addr_b[0:9]] <= data_b;
+        q_b <= data_b;
+      end else begin
         q_b <= ram_b[addr_b[0:9]];
-      end 
+      end
     // Operating mode: dual port RAM 2048 x 16
     end else if (4'b1000 == mode) begin
       if (we_a) begin

From 6f55371d4b73299f4fc368f0b54a47dbe1e4d0d7 Mon Sep 17 00:00:00 2001
From: "mustafa.arslan" <arslan705@hotmail.com>
Date: Thu, 13 Oct 2022 13:53:32 +0300
Subject: [PATCH 3/4] Update
 k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml

Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
---
 ...em32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
index dc39b625c..1997ab1f3 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
@@ -298,18 +298,18 @@
          of the input/output of the 36x36 multiplier
       -->
     <pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[two_mult_9x9].mult_9x9_slice.mult_9x9" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="01" physical_pb_type_index_factor="0">
-      <port name="a" physical_mode_port="a[0:8]" physical_mode_pin_rotate_offset="9"/>
-      <port name="b" physical_mode_port="b[0:8]" physical_mode_pin_rotate_offset="9"/>
-      <port name="out" physical_mode_port="out[0:17]" physical_mode_pin_rotate_offset="18"/>
+      <port name="a" physical_mode_port="a[0:8]" physical_mode_port_rotate_offset="9"/>
+      <port name="b" physical_mode_port="b[0:8]" physical_mode_port_rotate_offset="9"/>
+      <port name="out" physical_mode_port="out[0:17]" physical_mode_port_rotate_offset="18"/>
     </pb_type>
     <!-- Bind the 18x18 multiplier to the physical 36x36 multiplier
          There are two 18x18 multipliers, each of which occupies part
          of the input/output of the 36x36 multiplier
       -->
     <pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[mult_18x18].mult_18x18_slice.mult_18x18" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="10" physical_pb_type_index_factor="0">
-      <port name="a" physical_mode_port="a[0:17]" physical_mode_pin_rotate_offset="18"/>
-      <port name="b" physical_mode_port="b[0:17]" physical_mode_pin_rotate_offset="18"/>
-      <port name="out" physical_mode_port="out[0:35]" physical_mode_pin_rotate_offset="36"/>
+      <port name="a" physical_mode_port="a[0:17]" physical_mode_port_rotate_offset="18"/>
+      <port name="b" physical_mode_port="b[0:17]" physical_mode_port_rotate_offset="18"/>
+      <port name="out" physical_mode_port="out[0:35]" physical_mode_port_rotate_offset="36"/>
     </pb_type>
     <!-- END physical pb_type binding in complex block dsp -->
     <!-- physical pb_type binding in complex block memory -->

From d7a253408d741b9581f5897e306c1936cd1f89c3 Mon Sep 17 00:00:00 2001
From: "mustafa.arslan" <arslan705@hotmail.com>
Date: Thu, 13 Oct 2022 14:00:59 +0300
Subject: [PATCH 4/4] Update
 k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml

Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
---
 ...er_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
index bd350e389..0fcbfba3f 100644
--- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
@@ -286,18 +286,18 @@
          of the input/output of the 32x32 multiplier
       -->
     <pb_type name="mult_32[two_divisible_mult_16x16].divisible_mult_16x16[two_mult_8x8].mult_8x8_slice.mult_8x8" physical_pb_type_name="mult_32[mult_32x32].mult_32x32_slice.mult_32x32" mode_bits="01" physical_pb_type_index_factor="0">
-      <port name="a" physical_mode_port="a[0:7]" physical_mode_pin_rotate_offset="8"/>
-      <port name="b" physical_mode_port="b[0:7]" physical_mode_pin_rotate_offset="8"/>
-      <port name="out" physical_mode_port="out[0:15]" physical_mode_pin_rotate_offset="16"/>
+      <port name="a" physical_mode_port="a[0:7]" physical_mode_port_rotate_offset="8"/>
+      <port name="b" physical_mode_port="b[0:7]" physical_mode_port_rotate_offset="8"/>
+      <port name="out" physical_mode_port="out[0:15]" physical_mode_port_rotate_offset="16"/>
     </pb_type>
     <!-- Bind the 16x16 multiplier to the physical 32x32 multiplier
          There are two 16x16 multipliers, each of which occupies part
          of the input/output of the 32x32 multiplier
       -->
     <pb_type name="mult_32[two_divisible_mult_16x16].divisible_mult_16x16[mult_16x16].mult_16x16_slice.mult_16x16" physical_pb_type_name="mult_32[mult_32x32].mult_32x32_slice.mult_32x32" mode_bits="10" physical_pb_type_index_factor="0">
-      <port name="a" physical_mode_port="a[0:15]" physical_mode_pin_rotate_offset="16"/>
-      <port name="b" physical_mode_port="b[0:15]" physical_mode_pin_rotate_offset="16"/>
-      <port name="out" physical_mode_port="out[0:31]" physical_mode_pin_rotate_offset="32"/>
+      <port name="a" physical_mode_port="a[0:15]" physical_mode_port_rotate_offset="16"/>
+      <port name="b" physical_mode_port="b[0:15]" physical_mode_port_rotate_offset="16"/>
+      <port name="out" physical_mode_port="out[0:31]" physical_mode_port_rotate_offset="32"/>
     </pb_type>
     <!-- END physical pb_type binding in complex block dsp -->
   </pb_type_annotations>