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[arch] fixed a few bugs

This commit is contained in:
tangxifan 2022-05-09 17:22:48 +08:00
parent 9f56e61342
commit 7ed1548c6e
3 changed files with 32 additions and 4 deletions
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2
openfpga_flow/openfpga_arch/k4_frac_N4_fracff2edge_40nm_cc_openfpga.xml
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@ -220,7 +220,7 @@
</pb_type>
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="MULTI_MODE_DFFRQ" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="MULTI_MODE_DFFNRQ" mode_bits="00"/>
<!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->

6
openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
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@ -55,13 +55,13 @@ module \$_DFF_N_ (D, CN, Q);
dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(CN));
endmodule
module \$_DFF_NP0_ (D, CN, R, Q);
module \$_DFF_NP0_ (D, C, R, Q);
input D;
input CN;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(CN), .R(R));
dffnr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .CN(C), .R(R));
endmodule
module \$_DFFE_NP0P_ (D, C, E, R, Q);

28
openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
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@ -47,6 +47,34 @@ module dffr(
endcase
endmodule
(* abc9_flop, lib_whitebox *)
module dffnr(
output reg Q,
input D,
input R,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input CN
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge CN or posedge R)
if (R == 1'b1)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge CN or posedge R)
if (R == 1'b1)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
(* abc9_flop, lib_whitebox *)
module dffre(
output reg Q,