[benchmark] fixed a bug which causes yosys failed

openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v

@@ -12,7 +12,7 @@ input wire a;
 input wire b;
 output reg out;
 
-always @(rst or posedge clk) begin
+always @(posedge rst or posedge clk) begin
   if (rst) begin
     out <= 0;
   end else begin