From 314f5395b444d3b62efe4735cc1ca0d34c19666b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 9 Sep 2022 17:04:59 -0700 Subject: [PATCH] [benchmark] fixed a bug which causes yosys failed --- .../benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v b/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v index 25aafe763..95fc3d88d 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v +++ b/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v @@ -12,7 +12,7 @@ input wire a; input wire b; output reg out; -always @(rst or posedge clk) begin +always @(posedge rst or posedge clk) begin if (rst) begin out <= 0; end else begin