Claire Wolf
ab8826ae36
Merge pull request #1709 from rqou/coolrunner2_counter
...
Improve CoolRunner-II optimization by using extract_counter pass
2020-02-27 19:05:56 +01:00
Claire Wolf
47228feb77
Merge pull request #1708 from rqou/coolrunner2-buf-fix
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coolrunner2: Separate and improve buffer cell insertion pass
2020-02-27 19:03:59 +01:00
Piotr Binkowski
62ab100c61
xilinx: mark IOBUFDSE3 IOB pin as external
2020-02-27 13:15:57 +01:00
Marcus Comstedt
48a9b4f616
ecp5: Add missing parameter to \$__ECP5_PDPW16KD
2020-02-22 15:51:25 +01:00
R. Ou
13d0ff4a5f
coolrunner2: Use extract_counter to optimize counters
...
This tends to make much more efficient pterm usage compared to just
throwing the problem at ABC
2020-02-17 03:09:40 -08:00
R. Ou
6a0682f5a0
coolrunner2: Separate and improve buffer cell insertion pass
...
The new pass will contain all of the logic for inserting "passthrough"
product term and XOR cells as appropriate for the architecture. For
example, this commit fixes connecting an input pin directly to another
output pin with no logic in between.
2020-02-16 20:25:46 -08:00
Miodrag Milanovic
cd5c177739
Remove executable flag from files
2020-02-15 10:36:44 +01:00
Eddie Hung
00d41905df
abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr
2020-02-13 12:33:58 -08:00
Eddie Hung
c244b27b6d
abc9: cleanup
2020-02-10 10:17:23 -08:00
Eddie Hung
2e8d6ec0b0
Remove unnecessary comma
2020-02-07 12:45:07 -08:00
Eddie Hung
affae35847
techmap: fix shiftx2mux decomposition
2020-02-07 11:02:48 -08:00
Marcin Kościelnicki
89adef352f
xilinx: Add support for LUT RAM on LUT4-based devices.
...
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.
Fixes #1549
2020-02-07 09:03:22 +01:00
Marcin Kościelnicki
d48950d92d
xilinx: Initial support for LUT4 devices.
...
Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.
Fixes #1547
2020-02-07 09:03:22 +01:00
Eddie Hung
1f54b0008f
Merge pull request #1685 from dh73/gowin
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Removing cells_sim from GoWin bram techmap
2020-02-06 20:59:21 -08:00
Marcin Kościelnicki
30854b9c7f
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
Marcin Kościelnicki
95c46ccc55
xilinx: Add support for Spartan 3A DSP block RAMs.
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Part of #1550
2020-02-07 01:00:29 +01:00
Eddie Hung
1784d25f53
Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_map
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Fix/cleanup +/xilinx/arith_map.v
2020-02-06 13:51:23 -08:00
Diego H
87883f6d88
Removing cells_sim.v from bram techmap pass
2020-02-06 14:38:29 -06:00
Eddie Hung
d625e399cb
Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk
2020-02-06 11:25:07 -08:00
Eddie Hung
5ecbc6c7b2
Fix/cleanup +/xilinx/arith_map.v
2020-02-06 11:00:04 -08:00
whitequark
081d9318bc
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
...
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 16:52:51 +00:00
whitequark
3f4460a186
ice40: match memory inference attribute values case insensitive.
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LSE/Synplify use case insensitive matching.
2020-02-06 14:58:20 +00:00
whitequark
fc28bf55aa
ice40: add support for both 1364.1 and LSE RAM/ROM attributes.
...
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify appear to interpret attribute values insensitive
to case. There is currently no way to do this in Yosys (attrmap
can only change case of attribute names).
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 14:58:20 +00:00
Eddie Hung
0b0148399c
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00
Eddie Hung
4c1d3a126d
shiftx2mux: fix select out of bounds
2020-02-05 16:41:09 -08:00
Eddie Hung
b6a1f627b5
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
2020-02-05 10:47:31 -08:00
Eddie Hung
0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required
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abc9: add support for required times
2020-02-05 18:59:40 +01:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. ( #1673 )
2020-02-03 14:57:17 +01:00
Marcin Kościelnicki
b44d0e041f
xilinx: use RAM32M/RAM64M for memories with two read ports
...
This fixes inefficient LUT RAM usage for memories with one write
and two read ports (commonly used as register files).
2020-02-02 14:34:21 +01:00
Claire Wolf
5f53ea2b5b
Merge pull request #1659 from YosysHQ/clifford/experimental
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Add log_experimental() and experimental() API and "yosys -x"
2020-01-29 15:25:03 +01:00
Eddie Hung
c5971cb16c
synth_xilinx: cleanup help
2020-01-28 17:48:43 -08:00
Eddie Hung
0fd64aab25
synth_xilinx: fix help when no active_design; fixes #1664
2020-01-28 17:41:57 -08:00
Marcin Kościelnicki
7e0e42f907
xilinx: Add simulation model for DSP48 (Virtex 4).
2020-01-29 01:40:00 +01:00
Eddie Hung
7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
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Unpermute LUT ordering for ice40/ecp5/xilinx
2020-01-28 11:55:51 -08:00
Eddie Hung
245b8c4ab6
Fix unresolved conflict from #1573
2020-01-28 10:17:47 -08:00
N. Engelhardt
086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
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synth_xilinx: error out if tristate without '-iopad'
2020-01-28 17:24:54 +01:00
Eddie Hung
e18aeda7ed
Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
...
Just like Verilog...
2020-01-27 14:02:13 -08:00
Eddie Hung
cfb0366a18
Import tests from #1628
2020-01-27 13:56:16 -08:00
Eddie Hung
ce6a690d27
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
...
Now done in read_aiger
2020-01-27 13:30:27 -08:00
Eddie Hung
48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
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Refactor `abc9` pass
2020-01-27 13:29:15 -08:00
Eddie Hung
f2576c096c
Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
2020-01-27 12:29:28 -08:00
Eddie Hung
af8281d2f5
Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings
...
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-27 09:54:04 -08:00
Claire Wolf
cef607c8b7
Add log_experimental() and experimental() API and "yosys -x"
...
Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-27 18:27:47 +01:00
Eddie Hung
81e6b040a4
ice40: add SB_SPRAM256KA arrival time
2020-01-24 12:17:09 -08:00
Eddie Hung
b178761551
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-24 11:59:48 -08:00
Eddie Hung
7858cf20a9
Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
2020-01-23 19:02:27 -08:00
Eddie Hung
da134701cd
Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
2020-01-22 14:22:03 -08:00
Eddie Hung
72e4540ca9
Explicitly create separate $mux cells
2020-01-21 16:49:34 -08:00
Eddie Hung
3d9737c1bd
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-21 16:27:40 -08:00
Eddie Hung
152dfd3dd4
Fix tests -- when Y_WIDTH is non-pow-2
2020-01-21 15:19:41 -08:00
Eddie Hung
8d1b736c4f
Move from +/shiftx2mux.v into +/techmap.v; cleanup
2020-01-21 15:19:41 -08:00
Eddie Hung
7977574995
New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC
2020-01-21 15:19:41 -08:00
Eddie Hung
b7be6cfd65
Merge pull request #1643 from YosysHQ/eddie/cleanup_arith_map
...
Cleanup +/xilinx/arith_map.v
2020-01-18 09:11:52 -08:00
David Shah
a4cfd1237f
Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warning
...
ice40: Demote conflicting FF init values to a warning
2020-01-18 09:47:17 +00:00
Eddie Hung
78ffd5d193
synth_ice40: call wreduce before mul2dsp
2020-01-17 15:41:55 -08:00
Eddie Hung
5c589244df
Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623
2020-01-17 12:02:46 -08:00
Eddie Hung
1e6d56dca1
+/xilinx/arith_map.v fix $lcu rule
2020-01-17 11:28:37 -08:00
Eddie Hung
b0605128b6
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-15 16:42:27 -08:00
Eddie Hung
03ce2c72bb
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-15 16:42:16 -08:00
Eddie Hung
5a63c19747
abc9_ops: -write_box is empty, output a dummy box to prevent ABC error
2020-01-15 13:14:48 -08:00
Miodrag Milanović
abba1541bc
Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W
...
synth_xilinx: fix default W value for non-xc7
2020-01-15 08:47:16 +01:00
Eddie Hung
0e4285ca0d
abc9_ops: generate flop box ids, add abc9_required to FD* cells
2020-01-14 15:05:49 -08:00
Eddie Hung
915e7dde73
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-14 12:57:56 -08:00
Eddie Hung
d21262ee04
Adding (* techmap_autopurge *) to FD* in abc9_map.v
2020-01-14 12:22:21 -08:00
Eddie Hung
36d1a2c60f
synth_xilinx: fix default W value for non-xc7
2020-01-14 11:34:40 -08:00
Miodrag Milanović
9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr
...
Export wire properties in EDIF
2020-01-14 19:19:32 +01:00
Eddie Hung
ca2f3db53f
Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad
...
abc9: add some scripts/options into "scratchpad"
2020-01-13 09:04:20 -08:00
Eddie Hung
f9aae90e7a
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-12 15:19:41 -08:00
Eddie Hung
c0b55deb0b
synth_ice40: -abc2 to always use `abc` even if `-abc9`
2020-01-12 11:26:05 -08:00
Eddie Hung
35e49fde4d
Another conflict
2020-01-11 18:57:25 -08:00
Eddie Hung
c063436eea
Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad
2020-01-11 17:02:20 -08:00
Eddie Hung
28f814ee59
Add abc9_required to DSP48E1.{A,B,C,D,PCIN}
2020-01-10 17:12:31 -08:00
Eddie Hung
7d94e18100
synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro
2020-01-10 15:07:46 -08:00
Eddie Hung
475d983676
abc9_ops -prep_times: generate flop boxes from abc9_required attr
2020-01-10 14:49:52 -08:00
Eddie Hung
b2259a9201
Add abc9_ops -check, -prep_times, -write_box for required times
2020-01-10 11:45:41 -08:00
Miodrag Milanovic
992b507537
Use CARRY4 for abc1 as well, preventing issues with Vivado
2020-01-10 12:34:21 +01:00
Eddie Hung
57f6826e29
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-08 18:30:20 -08:00
Eddie Hung
823a08e0d8
Fix abc9_xc7.box comments
2020-01-07 17:00:38 -08:00
Eddie Hung
6e3e814025
Fix abc9_xc7.box comments
2020-01-07 15:59:18 -08:00
Eddie Hung
94ab3791ce
Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs
2020-01-07 15:44:18 -08:00
Eddie Hung
5c89dead5f
Merge branch 'master' of github.com:YosysHQ/yosys
2020-01-06 16:51:32 -08:00
Eddie Hung
01866a7909
Fix DSP48E1 sim
2020-01-06 16:45:29 -08:00
Eddie Hung
53aa51dc92
Re-enable &mfs for synth_{ecp5,xilinx}
2020-01-06 16:21:04 -08:00
Eddie Hung
98ee8c14df
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-06 15:02:44 -08:00
Eddie Hung
66698cb6fd
Merge pull request #1617 from YosysHQ/eddie/abc9_dsp_refactor
...
Refactor abc9's DSP48E1 handling
2020-01-06 15:00:16 -08:00
Eddie Hung
28bf712372
Wrap arrival functions inside `YOSYS too
2020-01-06 11:55:56 -08:00
Eddie Hung
27c150bfcc
Fix return value of arrival time functions, fix word
2020-01-06 11:39:08 -08:00
Eddie Hung
020606f81c
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_required
2020-01-06 09:44:00 -08:00
Eddie Hung
19541640ee
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-06 09:31:28 -08:00
Miodrag Milanovic
c5d28f5d6b
Valid to have attribute starting with SB_CARRY.
2020-01-04 19:00:44 +01:00
Eddie Hung
bac1e65a9c
Fix spacing
2020-01-02 17:21:54 -08:00
Eddie Hung
c28bea0382
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2020-01-02 15:57:35 -08:00
Eddie Hung
5f97086302
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-02 15:14:12 -08:00
Eddie Hung
50b68777d3
Drive $[ABCD] explicitly
2020-01-02 13:28:37 -08:00
whitequark
f8d5920a7e
Merge pull request #1604 from whitequark/unify-ram-naming
...
Harmonize BRAM/LUTRAM descriptions across all of Yosys
2020-01-02 21:06:17 +00:00
Eddie Hung
a051801b72
synth_xilinx -dff to work with abc too
2020-01-02 12:53:26 -08:00
Eddie Hung
3012e9eebc
Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor
2020-01-02 12:48:07 -08:00
Eddie Hung
b454735bea
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-02 12:44:06 -08:00
Eddie Hung
ec1756c094
Update comments
2020-01-02 12:39:52 -08:00
Eddie Hung
8e507bd807
abc9 -keepff -> -dff; refactor dff operations
2020-01-02 12:36:54 -08:00
Eddie Hung
d6242be802
Merge pull request #1601 from YosysHQ/eddie/synth_retime
...
"abc -dff" to no longer retime by default
2020-01-02 08:46:24 -08:00
Eddie Hung
d0d3ab8f67
ifndef __ICARUS__ -> ifdef YOSYS
2020-01-01 17:33:47 -08:00
Eddie Hung
3d98a96273
ifdef __ICARUS__ -> ifndef YOSYS
2020-01-01 17:33:10 -08:00
Eddie Hung
db04161eca
Rework abc9's DSP48E1 model
2020-01-01 17:30:26 -08:00
Eddie Hung
3deec51ddc
Fix anlogic async flop mapping
2020-01-01 08:43:16 -08:00
Eddie Hung
0e95756e96
Clamp -46ps for FDPE* too
2020-01-01 08:39:00 -08:00
Eddie Hung
c40b1aae42
Restore abc9 -keepff
2020-01-01 08:34:43 -08:00
whitequark
550310e264
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
...
This commit:
* renames all remaining instances of "DRAM" (which is ambiguous)
to "LUTRAM" (which is not), finishing the work started in
the commit 698ab9be;
* renames memory rule files to brams.txt/lutrams.txt;
* adds/renames script labels map_bram/map_lutram;
* extracts where necessary script labels map_ffram and map_gates;
* adds where necessary options -nobram/-nolutram.
The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.
Per architecture:
* anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
:map_lutram, :map_ffram, :map_gates
* ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
* efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
:map_gates
* gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
rename -nodram→-nolutram (-nodram still recognized), rename
:bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
2020-01-01 12:30:00 +00:00
Eddie Hung
44d9fb0e7c
Re-arrange FD order
2019-12-31 18:47:38 -08:00
Eddie Hung
f7793a2956
Missing character
2019-12-31 18:42:11 -08:00
Eddie Hung
35c659be74
Cleanup xilinx boxes
2019-12-31 18:29:44 -08:00
Eddie Hung
2358320f51
Cleanup ice40 boxes
2019-12-31 18:29:37 -08:00
Eddie Hung
b2046a2114
Cleanup ecp5 boxes
2019-12-31 18:29:29 -08:00
Eddie Hung
6b825c719b
Update abc9_xc7.box comments
2019-12-31 15:25:46 -08:00
Eddie Hung
4cdba00e25
FDCE ports to be alphabetical
2019-12-31 15:24:02 -08:00
Eddie Hung
b4663a987b
Fix attributes on $__ABC9_ASYNC[01] whitebox
2019-12-31 11:14:11 -08:00
Eddie Hung
789211d9b3
Fix incorrect $__ABC9_ASYNC[01] box
2019-12-31 11:13:50 -08:00
Niklas Nisbeth
379dcda139
ice40: Demote conflicting FF init values to a warning
2019-12-31 02:38:10 +01:00
Eddie Hung
7649ec72c9
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2019-12-30 16:20:58 -08:00
Eddie Hung
543bd2de6c
Update timings for Xilinx S7 cells
2019-12-30 14:36:07 -08:00
Eddie Hung
eb4e767053
Do not offset FD* box timings due to -46ps Tsu
2019-12-30 14:35:10 -08:00
Eddie Hung
405e974fe5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 14:31:42 -08:00
Eddie Hung
a038294a87
Tidy up abc9_map.v
2019-12-30 14:19:29 -08:00
Eddie Hung
d7ada66497
Add "synth_xilinx -dff" option, cleanup abc9
2019-12-30 14:13:16 -08:00
Eddie Hung
79448f9be0
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
Eddie Hung
c9e3b26412
Disable synth_gowin -abc9 as it offers no advantages yet
2019-12-30 13:28:29 -08:00
Eddie Hung
aa6d06c1b5
Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""
...
This reverts commit 6008bb7002
.
2019-12-30 13:28:29 -08:00
Miodrag Milanović
c0a17c2457
Merge pull request #1589 from YosysHQ/iopad_default
...
Make iopad option default for all xilinx flows
2019-12-30 20:34:31 +01:00
Miodrag Milanovic
8c3de1d4bd
Merge remote-tracking branch 'origin/master' into iopad_default
2019-12-28 16:23:31 +01:00
Eddie Hung
71906fab51
Nitpick cleanup for ecp5
2019-12-27 16:57:08 -08:00
Eddie Hung
b7afafde22
Consistency
2019-12-27 14:52:26 -08:00
Eddie Hung
4eaa45091c
Update some abc9_arrival times, add abc9_required times
2019-12-27 14:47:50 -08:00
Marcin Kościelnicki
13a3041030
Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-25 16:18:44 +01:00
Marcin Kościelnicki
dadaf7ed78
xilinx: Test our DSP48A/DSP48A1 simulation models.
2019-12-23 20:36:43 +01:00
Marcin Kościelnicki
666c6128a9
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
Miodrag Milanovic
436fea9e69
Addressed review comments
2019-12-21 20:23:23 +01:00
Miodrag Milanovic
1937091f62
iopad no op for compatibility with old scripts
2019-12-21 13:21:45 +01:00
Miodrag Milanovic
2fcf683af4
Make iopad option default for all xilinx flows
2019-12-21 11:56:41 +01:00
Eddie Hung
d3fc94405f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 14:07:23 -08:00
Eddie Hung
5986a4df40
Add abc9_arrival times for RAM{32,64}M
2019-12-20 14:06:59 -08:00
Eddie Hung
1ea1e8e54f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 13:56:13 -08:00
Eddie Hung
7928eb113c
Add RAM{32,64}M to abc9_map.v
2019-12-20 13:41:23 -08:00
Eddie Hung
10e82e103f
Revert "Optimise write_xaiger"
2019-12-20 12:05:45 -08:00
Eddie Hung
45f0f1486b
Add RAM{32,64}M to abc9_map.v
2019-12-19 11:24:39 -08:00
Eddie Hung
979bf36fb0
Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
2019-12-19 11:23:41 -08:00
Eddie Hung
94f15f023c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 10:29:40 -08:00
Eddie Hung
df626ee7ab
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
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Optimise write_xaiger
2019-12-19 12:24:03 -05:00
Marcin Kościelnicki
8b2c9f4518
xilinx: Add simulation models for remaining CLB primitives.
2019-12-19 18:04:04 +01:00
Marcin Kościelnicki
561ae1c5c4
xilinx_dffopt: Keep order of LUT inputs.
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See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
2019-12-19 18:01:43 +01:00
David Shah
520f1646cf
Merge pull request #1563 from YosysHQ/dave/async-prld
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ecp5: Add support for mapping PRLD FFs
2019-12-18 19:42:17 +00:00
Marcin Kościelnicki
a235250403
xilinx: Add xilinx_dffopt pass ( #1557 )
2019-12-18 13:43:43 +01:00
Marcin Kościelnicki
aff6ad1ce0
xilinx: Improve flip-flop handling.
...
This adds support for infering more kinds of flip-flops:
- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable
Some passes have been moved (and some added) in order for dff2dffs to
work correctly.
This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities). Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
2019-12-18 13:43:43 +01:00
Eddie Hung
a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
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xilinx: add LUTRAM rules for RAM32M, RAM64M
2019-12-16 21:48:21 -08:00
Eddie Hung
5a00d5578c
Add unconditional match blocks for force RAM
2019-12-16 13:31:15 -08:00
Eddie Hung
d910bec8e0
Update xc7/xcu bram rules
2019-12-16 13:00:58 -08:00
Eddie Hung
5d00996426
Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram
2019-12-16 12:06:47 -08:00
Eddie Hung
7545ab3814
Populate DID/DOD even if unused
2019-12-16 11:57:04 -08:00
Eddie Hung
c4d37813cb
Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q
2019-12-16 10:41:13 -08:00
Diego H
f3f59910eb
Removing fixed attribute value to !ramstyle rules
2019-12-15 23:51:58 -06:00
Diego H
b35559fc33
Merging attribute rules into a single match block; Adding tests
2019-12-15 23:33:09 -06:00
Diego H
266993408a
Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific
2019-12-13 15:43:24 -06:00
Eddie Hung
52875b0d61
Merge pull request #1533 from dh73/bram_xilinx
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Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
2019-12-13 12:01:03 -08:00
Eddie Hung
c3262d6075
Disable RAM16X1D match rule; carry-over from LUT4 arches
2019-12-13 08:59:17 -08:00
Eddie Hung
d6514fc2e1
RAM64M8 to also have [5:0] for address
2019-12-13 08:54:19 -08:00
Eddie Hung
dd7d2d8db6
Duplicate tribuf call, credit to @mwkmwkmwk
2019-12-13 08:51:05 -08:00
Eddie Hung
8925bf4b96
Add RAM32X6SDP and RAM64X3SDP modes
2019-12-12 18:52:28 -08:00
Eddie Hung
50e0c83560
Fix RAM64M model to have 6 bit address bus
2019-12-12 18:52:03 -08:00
Eddie Hung
7a9d1be97d
Add memory rules for RAM16X1D, RAM32M, RAM64M
2019-12-12 17:44:59 -08:00
Diego H
751a18d7e9
Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
2019-12-12 17:32:58 -06:00
Eddie Hung
bea15b537b
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-12 14:57:17 -08:00
Eddie Hung
9ab1feeaf1
abc9_map.v: fix Xilinx LUTRAM
2019-12-12 14:56:52 -08:00
Eddie Hung
3eed8835b5
abc9_map.v: fix Xilinx LUTRAM
2019-12-12 14:56:15 -08:00
Eddie Hung
3bd623bb05
synth_xilinx: error out if tristate without '-iopad'
2019-12-12 14:33:33 -08:00
Diego H
937ec1ee78
Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
2019-12-12 13:50:36 -06:00
Diego H
ab6ac8327f
Merge https://github.com/YosysHQ/yosys into bram_xilinx
2019-12-12 13:40:05 -06:00
Eddie Hung
f022645cd2
Fix bitwidth mismatch; suppresses iverilog warning
2019-12-11 13:02:07 -08:00
David Shah
613334d9dc
Merge pull request #1564 from ZirconiumX/intel_housekeeping
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Intel housekeeping
2019-12-11 08:46:10 +00:00
Dan Ravensloft
85a14895ca
synth_intel: a10gx -> arria10gx
2019-12-10 13:48:10 +00:00
Dan Ravensloft
eab3272cde
synth_intel: cyclone10 -> cyclone10lp
2019-12-10 13:47:58 +00:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
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Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
2019-12-09 17:38:48 -08:00
Eddie Hung
49c2e59b2a
Fix comment
2019-12-09 15:44:19 -08:00
Eddie Hung
fb203d2a2c
ice40_opt to restore attributes/name when unwrapping
2019-12-09 14:29:29 -08:00
Eddie Hung
500ed9b501
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
2019-12-09 12:45:22 -08:00
Eddie Hung
e05372778a
ice40_wrapcarry to really preserve attributes via -unwrap option
2019-12-09 11:48:28 -08:00
David Shah
184c0e796a
ecp5: Add support for mapping PRLD FFs
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Signed-off-by: David Shah <dave@ds0.me>
2019-12-07 13:04:36 +00:00
Eddie Hung
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
Eddie Hung
98c9ea605b
techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
2019-12-06 17:05:02 -08:00
Eddie Hung
c767525441
Remove creation of $abc9_control_wire
2019-12-06 16:23:09 -08:00
Eddie Hung
ec0acc9f85
abc9 to use mergeability class to differentiate sync/async
2019-12-06 00:12:37 -08:00
Eddie Hung
02786b0aa0
Remove clkpart
2019-12-05 17:25:26 -08:00
Eddie Hung
864bff14f1
Revert "Special abc9_clock wire to contain only clock signal"
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This reverts commit 6a2eb5d8f9
.
2019-12-05 11:11:53 -08:00
Eddie Hung
0d248dd7ba
Missing wire declaration
2019-12-04 23:04:40 -08:00
Eddie Hung
19bc429482
abc9_map.v to transform INIT=1 to INIT=0
2019-12-04 21:36:41 -08:00
Eddie Hung
258a34e6f1
Oh deary me
2019-12-04 20:33:24 -08:00
Eddie Hung
b43986c5a1
output reg Q -> output Q to suppress warning
2019-12-04 16:34:34 -08:00
Eddie Hung
31ef4cc704
abc9_map.v to do `zinit' and make INIT = 1'b0
2019-12-04 16:11:02 -08:00
Marcin Kościelnicki
fcce94010f
xilinx: Add tristate buffer mapping. ( #1528 )
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Fixes #1225 .
2019-12-04 09:44:00 +01:00
Marcin Kościelnicki
10014e2643
xilinx: Add models for LUTRAM cells. ( #1537 )
2019-12-04 06:31:09 +01:00
Eddie Hung
a181ff66d3
Add abc9_init wire, attach to abc9_flop cell
2019-12-03 18:47:09 -08:00
Eddie Hung
f98aa1c13f
Revert "Add INIT value to abc9_control"
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This reverts commit 19bfb41958
.
2019-12-03 15:40:44 -08:00
Eddie Hung
ed3f359175
$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve
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name and attr
2019-12-03 14:49:10 -08:00
Eddie Hung
1ea9ce0ad7
ice40_opt to ignore (* keep *) -ed cells
2019-12-03 14:48:39 -08:00
Eddie Hung
0add5965c7
techmap abc_unmap.v before xilinx_srl -fixed
2019-12-03 14:27:45 -08:00
Clifford Wolf
2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit
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Gowin: add and test DFF init values
2019-12-03 08:43:18 -08:00
Pepijn de Vos
a3b25b4af8
Use -match-init to not synth contradicting init values
2019-12-03 15:12:25 +01:00
Eddie Hung
19bfb41958
Add INIT value to abc9_control
2019-12-02 14:17:06 -08:00
Marcin Kościelnicki
2badaa9adb
xilinx: Add missing blackbox cell for BUFPLL.
2019-11-29 16:56:27 +01:00
Eddie Hung
b1ab7c16c4
clkpart -unpart into 'finalize'
2019-11-28 12:59:43 -08:00
Diego H
3a5a65829c
Adjusting Vivado's BRAM min bits threshold for RAMB18E1
2019-11-27 12:05:04 -06:00
Eddie Hung
df8dc6d1fb
ean call after abc{,9}
2019-11-27 09:10:34 -08:00
Eddie Hung
f6c0ec1d09
Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
2019-11-27 01:03:33 -08:00
Eddie Hung
739f530906
Move 'clean' from map_luts to finalize
2019-11-26 14:51:39 -08:00
Marcin Kościelnicki
0466c48533
xilinx: Add simulation models for IOBUF and OBUFT.
2019-11-26 08:15:20 +01:00
Eddie Hung
d087024caf
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 12:42:09 -08:00
Eddie Hung
6a2eb5d8f9
Special abc9_clock wire to contain only clock signal
2019-11-25 12:36:13 -08:00
Marcin Kościelnicki
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
Marcin Kościelnicki
7562e7304e
xilinx: Use INV instead of LUT1 when applicable
2019-11-25 20:40:39 +01:00
Pepijn de Vos
72d03dc910
attempt to fix formatting
2019-11-25 14:50:34 +01:00
Pepijn de Vos
6c79abbf5a
gowin: add and test dff init values
2019-11-25 14:33:21 +01:00
Eddie Hung
eb11c06a69
For abc9, run clkpart before ff_map and after abc9
2019-11-23 10:18:22 -08:00
Martin Pietryka
97b22413e5
coolrunner2: remove spurious log_pop() call, fixes #1463
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This was causing a segmentation fault because there is no accompanying
log_push() call so header_count.size() became -1.
Signed-off-by: Martin Pietryka <martin@pietryka.at>
2019-11-23 06:21:40 +01:00
Eddie Hung
bd56161775
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:38:48 -08:00
Marcin Kościelnicki
1d098b7195
gowin: Add missing .gitignore entries
2019-11-22 14:40:36 +01:00
Eddie Hung
5a30e3ac3b
Merge branch 'eddie/xaig_dff_adff' into xaig_dff
2019-11-21 16:15:25 -08:00
Eddie Hung
af3055fe83
Add blackbox model for $__ABC9_FF_ so that clock partitioning works
2019-11-20 14:30:56 -08:00
Eddie Hung
df63d75ff3
Fix INIT values
2019-11-20 11:26:59 -08:00
Eddie Hung
344619079d
Do not drop async control signals in abc_map.v
2019-11-19 16:57:07 -08:00
Eddie Hung
09ee96e8c2
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 15:40:39 -08:00
Clifford Wolf
7ea0a5937b
Merge pull request #1449 from pepijndevos/gowin
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Improvements for gowin support
2019-11-19 17:29:27 +01:00
Pepijn de Vos
8ab412eb16
Remove dff init altogether
...
The hardware does not actually support it.
In reality it is always initialised to its reset value.
2019-11-19 15:53:44 +01:00
Marcin Kościelnicki
7a9081440c
xilinx: Add simulation models for MULT18X18* and DSP48A*.
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This adds simulation models for the following primitives:
- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
2019-11-19 01:00:58 +01:00
Pepijn de Vos
dd8c7e1ddd
add help for nowidelut and abc9 options
2019-11-18 14:26:09 +01:00
Pepijn de Vos
32f0296df1
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
2019-11-16 12:43:17 +01:00
David Shah
51e4e29bb1
ecp5: Use new autoname pass for better cell/net names
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-15 21:03:11 +00:00
Clifford Wolf
e907ee4fde
Merge pull request #1490 from YosysHQ/clifford/autoname
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Add "autoname" pass and use it in "synth_ice40"
2019-11-14 18:03:44 +01:00
Clifford Wolf
056ef76711
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim
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ice40: Support for post-place-and-route timing simulations
2019-11-14 12:07:25 +01:00
Clifford Wolf
07c854b7af
Add "autoname" pass and use it in "synth_ice40"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-13 13:41:16 +01:00
Pepijn de Vos
ab8c521030
fix fsm test with proper clock enable polarity
2019-11-11 17:51:26 +01:00
Pepijn de Vos
ec3faa7b96
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
2019-11-11 17:08:40 +01:00
Clifford Wolf
362f4f996d
Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-11 15:07:29 +01:00
Pepijn de Vos
0e5dbc4abc
fix wide luts
2019-11-06 19:48:18 +01:00
Marcin Kościelnicki
c4bd318e76
synth_xilinx: Merge blackbox primitive libraries.
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First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-06 15:11:27 +01:00
Pepijn de Vos
0f6269b04c
add IOBUF
2019-10-28 15:33:05 +01:00
Pepijn de Vos
903f997391
add tristate buffer and test
2019-10-28 15:18:01 +01:00
Pepijn de Vos
2f5e9e9885
More formatting
2019-10-28 13:10:12 +01:00
Pepijn de Vos
c1921b4561
really really fix formatting maybe
2019-10-28 13:01:20 +01:00
Pepijn de Vos
293b2c2de5
undo formatting fuckup
2019-10-28 12:57:12 +01:00
Pepijn de Vos
f88335a8a5
add wide luts
2019-10-28 12:49:08 +01:00
Pepijn de Vos
5fad53b504
add 32-bit BRAM and byte-enables
2019-10-28 10:33:27 +01:00
Pepijn de Vos
8226f2db0b
ALU sim tweaks
2019-10-24 13:39:43 +02:00
David Shah
e135ed5d80
ice40: Add post-pnr ICESTORM_RAM model and fix FFs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 18:44:34 +01:00
David Shah
37dd3ad3fe
ice40: Support for post-pnr timing simulation
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 12:03:31 +01:00
David Shah
3506eaf290
xilinx: Add URAM288 mapping for xcup
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 11:47:44 +01:00
David Shah
6769d31ddb
xilinx: Add support for UltraScale[+] BRAM mapping
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 11:47:37 +01:00
Marcin Kościelnicki
7b350cacd4
xilinx: Support multiplier mapping for all families.
...
This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
2019-10-22 18:06:57 +02:00
Clifford Wolf
a3a7bb9bf7
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
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Call memory_dff before DSP mapping to reserve registers (fixes #1447 )
2019-10-22 17:36:54 +02:00
Pepijn de Vos
03457ee13e
add a few more missing dff
2019-10-21 16:08:13 +02:00
Pepijn de Vos
8a2699c40c
add negedge DFF
2019-10-21 12:31:11 +02:00
Pepijn de Vos
af7bdd598e
use ADDSUB ALU mode to remove inverters
2019-10-21 12:00:27 +02:00
Pepijn de Vos
69fb3b8db2
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
2019-10-21 10:51:34 +02:00
David Shah
fa989e59e5
ecp5: Pass -nomfs to abc9
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Fixes #1459
Signed-off-by: David Shah <dave@ds0.me>
2019-10-20 10:30:41 +01:00
Sean Cross
82f60ba938
Makefile: don't assume python is called `python3`
...
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`. The build system assumes
that python is called `python3`, which breaks under this architecture.
There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS. Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.
Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-19 14:04:52 +08:00
Miodrag Milanović
b4d7650548
Merge branch 'master' into mmicko/efinix
2019-10-18 10:54:28 +02:00
N. Engelhardt
3b405d985e
Call memory_dff before DSP mapping to reserve registers ( fixes #1447 )
2019-10-17 21:33:54 +02:00
Pepijn de Vos
72323e11a4
remove duplicate DFFR
2019-10-16 11:24:56 +02:00
David Shah
e1d4e683b4
ecp5: Add ECLKBRIDGECS blackbox
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-11 14:50:33 +01:00
David Shah
7b1a6706d8
ecp5: Add attrmvcp to copy syn_useioff to driving FF
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-10 15:58:31 +01:00
David Shah
3b44e80d4b
ecp5: Set syn_useioff on IO FFs to enable packing
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-10 15:55:16 +01:00
Marcin Kościelnicki
526fe4cb89
xilinx: Add simulation model for IBUFG.
2019-10-10 13:16:03 +02:00
Eddie Hung
304e5f9ea4
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-08 13:03:06 -07:00
Eddie Hung
9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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Rename abc_* names/attributes to more precisely be abc9_*
2019-10-08 10:53:38 -07:00
Eddie Hung
4f0818275f
Cleanup
2019-10-07 15:58:55 -07:00
Eddie Hung
b2e34f932a
Rename $currQ to $abc9_currQ
2019-10-07 15:31:43 -07:00
Eddie Hung
bae3d8705d
Update comments in abc9_map.v
2019-10-07 12:54:45 -07:00
Eddie Hung
1dc22607c3
Remove -D_ABC9
2019-10-07 12:21:52 -07:00
Eddie Hung
3879ca1398
Do not require changes to cells_sim.v; try and work out comb model
2019-10-05 22:55:18 -07:00
Eddie Hung
6c5e1234e1
Add comment on why partial multipliers are 18x18
2019-10-04 22:31:04 -07:00
Eddie Hung
b47bb5c810
Fix typo in check_label()
2019-10-04 21:43:50 -07:00
Eddie Hung
a2ef93f03a
abc -> abc9
2019-10-04 17:56:38 -07:00
Eddie Hung
a5ac33f230
Merge branch 'master' into eddie/abc_to_abc9
2019-10-04 17:53:20 -07:00
Eddie Hung
bbc0e06af3
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-04 17:39:08 -07:00
Eddie Hung
0acc51c3d8
Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`
2019-10-04 17:35:43 -07:00
Eddie Hung
d4212d128b
Use read_args for read_verilog
2019-10-04 17:27:05 -07:00
Eddie Hung
9c23811839
Remove DSP48E1 from *_cells_xtra.v
2019-10-04 17:26:42 -07:00
Eddie Hung
7959e9d6b2
Fix merge issues
2019-10-04 17:21:14 -07:00
Eddie Hung
7a45cd5856
Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
2019-10-04 16:58:55 -07:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Eddie Hung
9fef1df3c1
Panic over. Model was elsewhere. Re-arrange for consistency
2019-10-04 10:48:44 -07:00
Eddie Hung
4e11782cde
Oops
2019-10-04 10:36:02 -07:00
Eddie Hung
c0f54d3fd5
Ohmilord this wasn't added all this time!?!
2019-10-04 10:34:16 -07:00
Miodrag Milanovic
44c3472b9f
FF should be initialized to 0
2019-10-04 13:27:10 +02:00
Miodrag Milanovic
77d557d00b
Add missing latch mapping
2019-10-04 12:58:11 +02:00
Eddie Hung
549d6ea467
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-03 10:55:23 -07:00
Eddie Hung
655f1b2ac5
English
2019-10-03 10:11:25 -07:00
Eddie Hung
5299884f04
More fixes
2019-10-01 13:41:08 -07:00
Eddie Hung
03ebe43e3e
Escape Verilog identifiers for legality outside of Yosys
2019-10-01 13:05:56 -07:00
David Shah
b424d374db
ecp5: Fix shuffle_enable port
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-01 14:14:46 +01:00
David Shah
7a1538cd36
ecp5: Add support for mapping 36-bit wide PDP BRAMs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-01 13:46:36 +01:00
Eddie Hung
e529872b01
Remove need for $currQ port connection
2019-09-30 16:33:40 -07:00
Eddie Hung
5e9ae90cbb
Add explanation to abc_map.v
2019-09-30 15:39:24 -07:00
Eddie Hung
8684b58bed
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-30 12:29:35 -07:00
Eddie Hung
5b5756b91e
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
2019-09-30 12:52:43 +02:00
Marcin Kościelnicki
4535f2c694
synth_xilinx: Support latches, remove used-up FF init values.
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Fixes #1387 .
2019-09-30 12:52:43 +02:00
Eddie Hung
f6203e6bd6
Missing endmodule
2019-09-29 21:55:53 -07:00
Eddie Hung
1123c09588
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 19:39:12 -07:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Eddie Hung
18ebb86edb
FDCE_1 does not have IS_CLR_INVERTED
2019-09-29 11:25:34 -07:00
Eddie Hung
f3e150d9a5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 09:21:51 -07:00
Eddie Hung
79b6edb639
Big rework; flop info now mostly in cells_sim.v
2019-09-28 23:48:17 -07:00
Eddie Hung
c372e7baf9
Fix box name
2019-09-27 18:49:45 -07:00
Eddie Hung
8f5710c464
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-27 15:14:31 -07:00
Eddie Hung
b3d8a60cbd
Re-order
2019-09-27 14:32:07 -07:00
Eddie Hung
90236025b7
Missing (* mul2dsp *) for sliceB
2019-09-27 14:21:47 -07:00
Eddie Hung
143f82def2
Missing an '&'
2019-09-26 11:13:08 -07:00
Eddie Hung
84825f9378
Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once
2019-09-26 10:45:14 -07:00
Eddie Hung
033aefc0f4
Typo
2019-09-26 10:34:14 -07:00
Eddie Hung
781dda6175
select once
2019-09-26 10:15:05 -07:00
Eddie Hung
27e5bf5aad
Stop trying to be too smart by prematurely optimising
2019-09-26 09:57:11 -07:00
Eddie Hung
35aaa8d73a
mul2dsp.v slice names
2019-09-25 22:58:55 -07:00
Eddie Hung
34aa3532fb
Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit
2019-09-25 17:26:47 -07:00
Eddie Hung
a4238637ac
Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"
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This reverts commit 234738b103
.
2019-09-25 17:25:44 -07:00
Eddie Hung
f4387e817c
Revert "No need for $__mul anymore?"
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This reverts commit 1d875ac76a
.
2019-09-25 17:24:11 -07:00
Eddie Hung
63940913d2
Only wreduce on t:$add
2019-09-25 17:22:04 -07:00
Eddie Hung
234738b103
Remove _TECHMAP_CELLTYPE_ check since all $mul
2019-09-25 16:51:31 -07:00
Eddie Hung
1d875ac76a
No need for $__mul anymore?
2019-09-25 14:06:21 -07:00
Eddie Hung
53ea5daa42
Call 'wreduce' after mul2dsp to avoid unextend()
2019-09-25 14:04:36 -07:00
Eddie Hung
93363c94a2
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
2019-09-25 10:33:16 -07:00
Eddie Hung
b41d2fb4e4
Add (* techmap_autopurge *) to abc_unmap.v too
2019-09-23 22:02:22 -07:00
Eddie Hung
11ac37733d
Add techmap_autopurge to outputs in abc_map.v too
2019-09-23 21:56:28 -07:00
Eddie Hung
27167848f4
Revert "Add a xilinx_finalise pass"
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This reverts commit 23d90e0439
.
2019-09-23 19:52:55 -07:00
Eddie Hung
0f53893104
Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"
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This reverts commit 67c2db3486
.
2019-09-23 19:52:55 -07:00
Eddie Hung
29db96fa1f
Revert "Vivado does not like zero width port connections"
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This reverts commit 895e2befa7
.
2019-09-23 19:52:54 -07:00
Eddie Hung
895e2befa7
Vivado does not like zero width port connections
2019-09-23 19:04:07 -07:00
Eddie Hung
67c2db3486
Remove (* techmap_autopurge *) from abc_unmap.v since no effect
2019-09-23 18:56:18 -07:00
Eddie Hung
23d90e0439
Add a xilinx_finalise pass
2019-09-23 18:56:02 -07:00
Eddie Hung
4401e5f142
Grammar
2019-09-20 14:24:31 -07:00
Eddie Hung
ab46d9017b
Fix signedness bug
2019-09-20 10:11:36 -07:00
Eddie Hung
289cf688b7
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
2019-09-20 09:02:29 -07:00
Eddie Hung
829e4f5d2c
Revert "Move mul2dsp before wreduce"
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This reverts commit e4f4f6a9d5
.
2019-09-20 08:56:16 -07:00
Eddie Hung
e4f4f6a9d5
Move mul2dsp before wreduce
2019-09-20 08:41:40 -07:00
Eddie Hung
691686f92c
Tidy up, fix undriven
2019-09-19 20:04:52 -07:00
Eddie Hung
1602516a8b
$__ABC_REG to have WIDTH parameter
2019-09-19 19:37:45 -07:00
Eddie Hung
e09f80479e
Fix DSP48E1 timing by breaking P path if MREG or PREG
2019-09-19 18:59:28 -07:00
Eddie Hung
362a803779
Revert "Different approach to timing"
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This reverts commit 41256f48a5
.
2019-09-19 18:33:38 -07:00
Eddie Hung
41256f48a5
Different approach to timing
2019-09-19 18:33:29 -07:00
Eddie Hung
5ca25b0c59
Suppress $anyseq warnings
2019-09-19 16:27:14 -07:00
Eddie Hung
595fb611a5
Use (* techmap_autopurge *) to suppress techmap warnings
2019-09-19 15:58:01 -07:00
Eddie Hung
c15a35db84
D is 25 bits not 24 bits wide
2019-09-19 15:55:49 -07:00
Eddie Hung
b88f0f6450
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
2019-09-19 15:47:41 -07:00
Eddie Hung
95db2489bd
synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2
2019-09-19 14:58:06 -07:00
Eddie Hung
3b9b0fcd06
Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2
2019-09-19 14:57:38 -07:00
Marcin Kościelnicki
13fa873f11
Use extractinv for synth_xilinx -ise
2019-09-19 04:02:48 +02:00
Eddie Hung
fd3b033903
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-18 12:23:22 -07:00
Eddie Hung
25e0f0c376
Fix copy-paste
2019-09-18 12:19:16 -07:00
Eddie Hung
b77cf6ba48
Mis-spell
2019-09-18 11:12:46 -07:00
Eddie Hung
e992dbf2c5
Add pattern detection support for DSP48E1 model, check against vendor
2019-09-18 10:45:04 -07:00
Eddie Hung
3ec28ec53a
Merge pull request #1379 from mmicko/sim_models
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Added simulation models for Efinix and Anlogic
2019-09-18 10:04:27 -07:00
Miodrag Milanovic
3e9449cb0b
make note that it is for latch mode
2019-09-18 17:48:16 +02:00
Miodrag Milanovic
b0ca6de472
better lut handling
2019-09-18 17:45:19 +02:00
Miodrag Milanovic
8badd4d812
better handling of lut and begin/end add
2019-09-18 17:45:07 +02:00
Marcin Kościelnicki
09ac36da60
xilinx: Make blackbox library family-dependent.
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Fixes #1246 .
2019-09-15 13:37:24 +02:00
Miodrag Milanovic
3487b95224
Added simulation models for Efinix and Anlogic
2019-09-15 09:37:16 +02:00
Eddie Hung
681be20ca2
Add `undef DSP48E1_INST
2019-09-13 17:07:18 -07:00
Eddie Hung
61877e1370
Fix D -> P{,COUT} delay
2019-09-13 13:32:55 -07:00
Eddie Hung
d0b202c58d
Add no MULT no DPORT config
2019-09-13 12:05:14 -07:00
Eddie Hung
247a63f55d
Add support for MULT and DPORT
2019-09-13 11:45:55 -07:00
Eddie Hung
e235dd0785
Refine diagram
2019-09-13 09:34:40 -07:00
Eddie Hung
734034a872
Add an ASCII drawing
2019-09-12 18:13:46 -07:00
Eddie Hung
c52863f147
Finish explanation
2019-09-12 18:01:49 -07:00
Eddie Hung
aaeaab4ac0
Rename to techmap_guard
2019-09-12 17:45:02 -07:00
Eddie Hung
6bb8e6a726
Initial DSP48E1 box support
2019-09-12 17:11:01 -07:00
Eddie Hung
3a39073302
Set more ports explicitly
2019-09-12 17:10:43 -07:00
Eddie Hung
0ebbecf833
Missing space
2019-09-11 13:06:59 -07:00
Eddie Hung
feb3fa65a3
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-11 00:01:31 -07:00
Eddie Hung
5c1271c51c
Move "(skip if -nodsp)" message to label
2019-09-10 15:26:56 -07:00
Eddie Hung
f2d030a70f
Be sensitive to signedness
2019-09-10 15:14:55 -07:00
Eddie Hung
76eedee089
Really get rid of 'opt_expr -fine' by being explicit
2019-09-10 14:26:12 -07:00
Eddie Hung
c460d10e60
Remove wreduce call
2019-09-10 14:17:35 -07:00
Eddie Hung
f3a55d3f06
Add comment for why opt_expr is necessary
2019-09-10 14:11:56 -07:00
Eddie Hung
8514e7c32e
Revert "Remove "opt_expr -fine" call"
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This reverts commit bfda921d03
.
2019-09-10 14:09:21 -07:00
Eddie Hung
d3fb308181
Rename label to map_dsp
2019-09-10 13:18:10 -07:00
Eddie Hung
bfda921d03
Remove "opt_expr -fine" call
2019-09-10 13:17:47 -07:00
Eddie Hung
a7e6032287
Set USE_MULT and USE_SIMD
2019-09-09 20:56:29 -07:00
Marcin Kościelnicki
fda94311ee
synth_xilinx: Support init values on Spartan 6 flip-flops properly.
2019-09-07 16:30:43 +02:00
Pepijn de Vos
2fb20f184a
Revert "add MUX support"
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It turns out that they make everything worse and they don't PnR.
This reverts commit 3eff2271d0
.
2019-09-06 11:28:17 +02:00
Pepijn de Vos
96efa63f16
fix BRAM width and init
2019-09-06 10:55:04 +02:00
Pepijn de Vos
1b9f7f49b5
add more DFF to sim lib
2019-09-06 09:01:07 +02:00
Eddie Hung
e742478e1d
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-05 13:01:27 -07:00
Pepijn de Vos
5168b6ffa4
WIP aditional DFF primitives
2019-09-05 19:12:47 +02:00
Pepijn de Vos
47374a495d
support bram initialisation
2019-09-05 17:25:51 +02:00
Pepijn de Vos
7a43be5e43
use singleton ground and vcc nets, apparently this makes pnr happier
2019-09-05 16:38:47 +02:00
Pepijn de Vos
3eff2271d0
add MUX support
2019-09-05 13:36:41 +02:00
Eddie Hung
aa1491add3
Resolve TODO with pin assignments for SRL*
2019-09-04 15:47:36 -07:00
Eddie Hung
3732d421c5
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-04 12:37:42 -07:00
Pepijn de Vos
ae93c034ad
set undriven pads to zero
2019-09-04 16:29:40 +02:00
Pepijn de Vos
a6d81a8d14
Merge remote-tracking branch 'diego/gowin'
2019-09-04 11:20:05 +02:00
Pepijn de Vos
ec56438cf2
gowin: add splitnets to appease the PnR
2019-09-04 10:33:47 +02:00
Diego H
5aa8d7ceeb
Updating gowin
2019-09-02 17:43:27 -05:00
Eddie Hung
3459d28349
Add comments
2019-09-02 12:22:15 -07:00
Eddie Hung
696f854801
Rename box
2019-09-02 12:15:11 -07:00
Eddie Hung
2fa3857963
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-09-02 12:13:44 -07:00
Miodrag Milanovic
a3c16a0565
Fix TRELLIS_FF simulation model
2019-08-31 11:12:06 +02:00
David Shah
90b44113d8
ecp5_gsr: Fix typo
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-31 09:58:46 +01:00
Eddie Hung
f33abd4eab
Remove trailing space
2019-08-30 16:44:11 -07:00
Eddie Hung
723815b384
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-30 13:26:19 -07:00
Eddie Hung
f0fef90e9d
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 10:30:46 -07:00
Eddie Hung
295c18bd6b
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-08-30 09:50:20 -07:00
Eddie Hung
6e475484b2
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-30 09:37:32 -07:00
David Shah
6919c0f9b0
Merge branch 'master' into xc7dsp
2019-08-30 13:57:15 +01:00
David Shah
91b46ed816
ecp5: Add simulation equivalence check for Diamond FF implementations
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-30 13:27:36 +01:00
whitequark
d9c621f9d1
ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives.
2019-08-30 10:05:09 +00:00
whitequark
1e6b60d563
ecp5: allow (and enable by default) GSR on FD/IFS/OFS primitives.
2019-08-30 09:56:19 +00:00
whitequark
6fa8ce93e6
ecp5: add missing FD primitives.
2019-08-30 09:54:48 +00:00
whitequark
7e2825a2a4
ecp5: fix CEMUX on IFS/OFS primitives.
2019-08-30 09:42:33 +00:00
Eddie Hung
25b1670a84
Rename boxes too
2019-08-29 07:03:32 -07:00
Eddie Hung
c4e5310823
Use a dummy box file if none specified
2019-08-28 20:58:55 -07:00
Eddie Hung
e8e3830868
Comment out SB_MAC16 arrival time for now, need to handle all its modes
2019-08-28 19:09:29 -07:00
Eddie Hung
309684af16
Add arrival for SB_MAC16.O
2019-08-28 19:07:28 -07:00
Eddie Hung
efa4ee5c0e
Add arrival times for U
2019-08-28 19:03:29 -07:00
Eddie Hung
4bda902f1b
LX -> LP
2019-08-28 19:02:54 -07:00
Eddie Hung
0f4e9f6bc5
Round not floor
2019-08-28 18:57:34 -07:00
Eddie Hung
927f1e3754
Add LP timings
2019-08-28 18:56:25 -07:00
Eddie Hung
e3709e5ee6
LX -> LP
2019-08-28 18:51:14 -07:00
Eddie Hung
a4f641f230
Do not overwrite LUT param
2019-08-28 18:46:53 -07:00
Eddie Hung
c0b99ed0e8
Do not overwrite LUT param
2019-08-28 18:45:09 -07:00
Eddie Hung
070f3ac561
Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival
2019-08-28 17:29:25 -07:00
Eddie Hung
d46d38e4d5
Trailing comma
2019-08-28 17:25:54 -07:00
Eddie Hung
f5b4bc847c
Adapt to $__ICE40_CARRY_WRAPPER
2019-08-28 17:25:05 -07:00
Eddie Hung
e569f13870
Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with"
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This reverts commit 2aedee1f0e
.
2019-08-28 17:22:44 -07:00
Eddie Hung
2421cb3fed
Add arrival times for HX devices
2019-08-28 17:21:37 -07:00
Eddie Hung
e4f89e01b5
Specify ice40 family to cells_sim.v using define
2019-08-28 17:21:12 -07:00
Eddie Hung
345a572449
Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival
2019-08-28 17:19:02 -07:00
Eddie Hung
2aedee1f0e
Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with
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CARRY_WRAPPER in the same way since I0 and I3 could be used
2019-08-28 17:07:36 -07:00
Eddie Hung
077e9d4ada
Update box size and timings
2019-08-28 17:07:24 -07:00
Eddie Hung
129df7184a
Update to new $__ICE40_CARRY_WRAPPER
2019-08-28 17:07:07 -07:00
Eddie Hung
1b08f861b6
Merge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-28 15:31:48 -07:00
Eddie Hung
8d820a9884
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-28 15:19:10 -07:00
Eddie Hung
9314a0a42e
Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
2019-08-28 10:51:39 -07:00
Eddie Hung
ba5d81c7f1
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-28 09:21:03 -07:00
David Shah
13424352cc
Merge pull request #1332 from YosysHQ/dave/ecp5gsr
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ecp5: Add GSR and SGSR support
2019-08-28 12:44:02 +01:00
Marcin Kościelnicki
d361f5ab79
xilinx: Add SRLC16E primitive.
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Fixes #1331 .
2019-08-27 20:27:12 +02:00
David Shah
fc001b4731
ecp5: Add GSR support
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-27 13:07:06 +01:00
Eddie Hung
1ba09c4ab7
Merge branch 'master' into eddie/xilinx_srl
2019-08-26 13:56:31 -07:00
Eddie Hung
a098205479
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-26 13:25:17 -07:00
Eddie Hung
d7051b90de
Add undocumented feature
2019-08-23 16:41:32 -07:00
Eddie Hung
455da57272
Fix spacing
2019-08-23 13:21:21 -07:00
Eddie Hung
85d39653ac
Remove unused model
2019-08-23 13:20:29 -07:00
Eddie Hung
08139aa53a
xilinx_srl now copes with word-level flops $dff{,e}
2019-08-23 12:22:46 -07:00
Eddie Hung
78b7d8f531
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-23 11:32:44 -07:00
Eddie Hung
e658d472c8
Put attributes above port
2019-08-23 11:31:20 -07:00
Eddie Hung
d672b1ddec
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-23 11:26:55 -07:00
Eddie Hung
20f4d191b5
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-23 11:24:19 -07:00
Eddie Hung
509c353fe9
Forgot one
2019-08-23 11:23:50 -07:00
Eddie Hung
0d0ad15898
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-23 11:23:31 -07:00
Eddie Hung
a270af00cc
Put abc_* attributes above port
2019-08-23 11:21:44 -07:00
Eddie Hung
6872805a3e
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
2019-08-23 10:00:50 -07:00
Eddie Hung
7188972645
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-22 10:32:54 -07:00
Clifford Wolf
151db528e4
Fix missing newline at end of file
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-22 18:09:37 +02:00
Clifford Wolf
2c8c8b3c74
Merge pull request #1289 from mmicko/anlogic_fixes
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Anlogic fixes and optimization
2019-08-22 18:09:10 +02:00
Clifford Wolf
4c449caf9b
Fix missing newline at end of file
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-22 18:06:36 +02:00
Clifford Wolf
4d37710e82
Merge pull request #1281 from mmicko/efinix
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Initial support for Efinix Trion series FPGAs
2019-08-22 18:06:02 +02:00
Eddie Hung
15188033da
Add variable length support to xilinx_srl
2019-08-21 17:34:40 -07:00
Eddie Hung
edec73fec1
abc9 to perform new 'map_ffs' before 'map_luts'
2019-08-21 15:37:55 -07:00
Eddie Hung
5ce0c31d0e
Add init support
2019-08-21 13:05:10 -07:00
Eddie Hung
c7af71ecde
Use semicolon
2019-08-21 11:47:17 -07:00
Eddie Hung
5d0f6cbd54
techmap before read
2019-08-21 11:47:06 -07:00
Eddie Hung
8f69be9cc7
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-21 11:39:14 -07:00
Eddie Hung
584c680691
Add abc_arrival to SRL*
2019-08-21 11:27:42 -07:00
Eddie Hung
076af2e617
Missing newline
2019-08-20 20:37:52 -07:00
Eddie Hung
b7a48e3e0f
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-20 20:18:17 -07:00
Eddie Hung
64d62710de
Oops
2019-08-20 20:07:38 -07:00
Eddie Hung
c26c556384
xilinx to use abc_map.v with -max_iter 1
2019-08-20 19:47:11 -07:00
Eddie Hung
6b1b03d9f7
ecp5: remove DPR16X4 from abc_unmap.v
2019-08-20 19:20:17 -07:00
Eddie Hung
d46dc9c5b4
ecp5 to use -max_iter 1
2019-08-20 19:18:36 -07:00
Eddie Hung
55acf3120f
ecp5 to use abc_map.v and _unmap.v
2019-08-20 18:59:03 -07:00
Eddie Hung
343039496b
Add reference to FD* timing
2019-08-20 18:22:58 -07:00
Eddie Hung
f1a206ba03
Revert "Remove sequential extension"
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This reverts commit 091bf4a18b
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2019-08-20 18:17:14 -07:00
Eddie Hung
091bf4a18b
Remove sequential extension
2019-08-20 18:16:37 -07:00
Eddie Hung
bbab608691
Remove SRL* delays from cells_sim.v
2019-08-20 18:14:40 -07:00
Eddie Hung
aa2d3af631
LUTMUX -> LUTMUX6
2019-08-20 18:08:07 -07:00
Eddie Hung
30a379b5b6
Cleanup techmap in map_luts
2019-08-20 17:59:31 -07:00
Eddie Hung
3b52d6e29c
Move `techmap abc_map.v` into map_luts
2019-08-20 17:55:12 -07:00
Eddie Hung
54284aaa98
Remove delays from abc_map.v
2019-08-20 17:52:27 -07:00
Eddie Hung
96f00e9147
Typo
2019-08-20 17:51:50 -07:00
Eddie Hung
8f666ebac1
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 17:36:14 -07:00
Eddie Hung
e273ed5275
Wrap SRL{16,32} too
2019-08-20 15:09:38 -07:00
Eddie Hung
808f07630f
Wrap LUTRAMs in order to capture comb/seq behaviour
2019-08-20 14:49:11 -07:00
Eddie Hung
0079e9b4a6
Add LUTRAM delays
2019-08-20 13:53:38 -07:00
Eddie Hung
8d0cffaf20
Remove mapping rules
2019-08-20 13:11:39 -07:00
Eddie Hung
33960dd3d8
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
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[WIP] synth xilinx renaming, as per #1184
2019-08-20 12:55:26 -07:00
Eddie Hung
5eda5fc7eb
Remove -icells
2019-08-20 12:41:11 -07:00
Eddie Hung
be9e4f1b67
Use abc_{map,unmap,model}.v
2019-08-20 12:39:11 -07:00
Eddie Hung
c4d4c6db3f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 12:00:12 -07:00
Eddie Hung
14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
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Refactor abc9 to use port attributes, not module attributes
2019-08-20 11:59:31 -07:00
Eddie Hung
d9fe4cccbf
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
2019-08-20 11:57:52 -07:00
Eddie Hung
526e081342
Add arrival times for SRL outputs
2019-08-19 15:15:43 -07:00
Eddie Hung
b71212ddea
Add BRAM arrival times
2019-08-19 12:46:35 -07:00
Eddie Hung
2f86366087
Add reference to source of Tclktoq timing
2019-08-19 12:39:22 -07:00
Eddie Hung
d02ef8c73f
Add 'abc_arrival' attribute for flop outputs
2019-08-19 11:32:18 -07:00
Eddie Hung
f25837f8e8
Update box timings
2019-08-19 11:31:40 -07:00