mirror of https://github.com/YosysHQ/yosys.git
parent
aeb1539818
commit
f4387e817c
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@ -49,7 +49,7 @@ $fatal(1, "Macro DSP_NAME must be defined");
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`define MAX(a,b) (a > b ? a : b)
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`define MIN(a,b) (a < b ? a : b)
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(* techmap_celltype = "$mul" *)
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(* techmap_celltype = "$mul $__mul" *)
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module _80_mul (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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@ -128,9 +128,9 @@ module _80_mul (A, B, Y);
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end
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for (i = 0; i < n; i=i+1) begin:slice
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\$mul #(
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\$__mul #(
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.A_SIGNED(sign_headroom),
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.B_SIGNED(sign_headroom),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(partial_Y_WIDTH)
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@ -157,7 +157,7 @@ module _80_mul (A, B, Y);
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end
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end
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\$mul #(
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(last_A_WIDTH),
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@ -193,8 +193,8 @@ module _80_mul (A, B, Y);
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end
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for (i = 0; i < n; i=i+1) begin:slice
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\$mul #(
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.A_SIGNED(sign_headroom),
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(sign_headroom),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL),
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@ -222,7 +222,7 @@ module _80_mul (A, B, Y);
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end
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end
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\$mul #(
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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@ -267,7 +267,7 @@ module _80_mul (A, B, Y);
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endgenerate
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endmodule
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(* techmap_celltype = "$mul" *)
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(* techmap_celltype = "$mul $__mul" *)
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module _90_soft_mul (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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