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Add init support

This commit is contained in:
Eddie Hung 2019-08-21 13:05:10 -07:00
parent df53fe12e7
commit 5ce0c31d0e
2 changed files with 12 additions and 3 deletions
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13
passes/pmgen/xilinx_srl.cc
View File

@ -42,20 +42,29 @@ void reduce_chain(xilinx_srl_pm &pm, int minlen)
auto last_cell = ud.longest_chain.back();
SigSpec initval;
for (auto cell : ud.longest_chain) {
log_debug(" %s\n", log_id(cell));
SigBit Q = cell->getPort(ID(Q));
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID(init));
if (it != Q.wire->attributes.end()) {
initval.append(it->second[Q.offset]);
}
else
initval.append(State::Sx);
if (cell != last_cell)
pm.autoremove(cell);
}
Cell *c = last_cell;
SigSpec Q = st.first->getPort(ID(Q));
SigBit Q = st.first->getPort(ID(Q));
c->setPort(ID(Q), Q);
if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
c->parameters.clear();
c->setParam(ID(DEPTH), GetSize(ud.longest_chain));
// TODO c->setParam(ID(INIT), init);
c->setParam(ID(INIT), initval.as_const());
if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
c->setParam(ID(CLKPOL), 1);
else

2
techlibs/xilinx/synth_xilinx.cc
View File

@ -406,7 +406,7 @@ struct SynthXilinxPass : public ScriptPass
// This shregmap call infers fixed length shift registers after abc
// has performed any necessary retiming
if (!nosrl || help_mode)
run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
run("xilinx_srl -minlen 3", "(skip if '-nosrl')");
run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");