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techmap before read

This commit is contained in:
Eddie Hung 2019-08-21 11:47:06 -07:00
parent d4d692989a
commit 5d0f6cbd54
1 changed files with 1 additions and 1 deletions
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2
techlibs/xilinx/synth_xilinx.cc
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@ -390,8 +390,8 @@ struct SynthXilinxPass : public ScriptPass
else if (abc9) {
if (family != "xc7")
log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
run("read_verilog -icells -lib +/xilinx/abc_model.v");
run("techmap -map +/xilinx/abc_map.v -max_iter 1");
run("read_verilog -icells -lib +/xilinx/abc_model.v");
if (nowidelut)
run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
else