mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor
This commit is contained in:
commit
3012e9eebc
|
@ -1893,10 +1893,6 @@ DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
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DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
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DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
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DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
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DEF_METHOD(Shl, sig_a.size(), ID($shl))
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DEF_METHOD(Shr, sig_a.size(), ID($shr))
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DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
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DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
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DEF_METHOD(Shift, sig_a.size(), ID($shift))
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DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
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DEF_METHOD(Lt, 1, ID($lt))
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@ -1916,6 +1912,31 @@ DEF_METHOD(LogicAnd, 1, ID($logic_and))
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DEF_METHOD(LogicOr, 1, ID($logic_or))
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#undef DEF_METHOD
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#define DEF_METHOD(_func, _y_size, _type) \
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RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
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RTLIL::Cell *cell = addCell(name, _type); \
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cell->parameters[ID(A_SIGNED)] = is_signed; \
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cell->parameters[ID(B_SIGNED)] = false; \
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cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
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cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
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cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
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cell->setPort(ID::A, sig_a); \
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cell->setPort(ID::B, sig_b); \
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cell->setPort(ID::Y, sig_y); \
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cell->set_src_attribute(src); \
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return cell; \
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} \
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RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
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RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
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add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
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return sig_y; \
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}
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DEF_METHOD(Shl, sig_a.size(), ID($shl))
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DEF_METHOD(Shr, sig_a.size(), ID($shr))
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DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
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DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
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#undef DEF_METHOD
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#define DEF_METHOD(_func, _type, _pmux) \
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RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
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RTLIL::Cell *cell = addCell(name, _type); \
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@ -29,17 +29,17 @@
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// Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558-562, doi:10.1145/368996.369025
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// http://en.wikipedia.org/wiki/Topological_sorting
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#define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put"
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#define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
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#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; dch -f; if; mfs2"
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#define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; dch -f; cover {I} {P}"
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#define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put"
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#define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
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#define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
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#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2"
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#define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}"
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#define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
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#define ABC_FAST_COMMAND_LIB "strash; dretime; retime {D}; map {D}"
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#define ABC_FAST_COMMAND_CTR "strash; dretime; retime {D}; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
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#define ABC_FAST_COMMAND_LUT "strash; dretime; retime {D}; if"
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#define ABC_FAST_COMMAND_SOP "strash; dretime; retime {D}; cover -I {I} -P {P}"
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#define ABC_FAST_COMMAND_DFL "strash; dretime; retime {D}; map"
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#define ABC_FAST_COMMAND_LIB "strash; dretime; map {D}"
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#define ABC_FAST_COMMAND_CTR "strash; dretime; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
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#define ABC_FAST_COMMAND_LUT "strash; dretime; if"
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#define ABC_FAST_COMMAND_SOP "strash; dretime; cover -I {I} -P {P}"
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#define ABC_FAST_COMMAND_DFL "strash; dretime; map"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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@ -747,6 +747,10 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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else
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abc_script += fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL;
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if (script_file.empty() && !delay_target.empty())
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for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
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abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
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for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
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abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
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@ -52,7 +52,7 @@ struct SynthAchronixPass : public ScriptPass {
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log(" run 'abc' with '-dff -D 1' options\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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@ -152,12 +152,12 @@ struct SynthAchronixPass : public ScriptPass {
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run("clean -purge");
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run("setundef -undriven -zero");
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if (retime || help_mode)
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run("abc -markgroups -dff", "(only if -retime)");
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run("abc -markgroups -dff -D 1", "(only if -retime)");
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}
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if (check_label("map_luts"))
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{
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run("abc -lut 4" + string(retime ? " -dff" : ""));
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run("abc -lut 4" + string(retime ? " -dff -D 1" : ""));
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run("clean");
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}
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@ -58,7 +58,7 @@ struct SynthAnlogicPass : public ScriptPass
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log(" run 'abc' with '-dff -D 1' options\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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@ -164,7 +164,7 @@ struct SynthAnlogicPass : public ScriptPass
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run("opt -undriven -fine");
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run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
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if (retime || help_mode)
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run("abc -dff", "(only if -retime)");
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run("abc -dff -D 1", "(only if -retime)");
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}
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if (check_label("map_ffs"))
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@ -55,7 +55,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log(" run 'abc' with '-dff -D 1' options\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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@ -161,7 +161,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
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if (check_label("map_pla"))
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{
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run("abc -sop -I 40 -P 56");
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run("abc -sop -I 40 -P 56" + string(retime ? " -dff -D 1" : ""));
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run("clean");
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}
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@ -56,7 +56,7 @@ struct SynthEasicPass : public ScriptPass
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log(" run 'abc' with '-dff -D 1' options\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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@ -158,7 +158,7 @@ struct SynthEasicPass : public ScriptPass
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run("techmap");
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run("opt -fast");
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if (retime || help_mode) {
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run("abc -dff", " (only if -retime)");
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run("abc -dff -D 1", " (only if -retime)");
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run("opt_clean", "(only if -retime)");
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}
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}
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@ -62,7 +62,7 @@ struct SynthEcp5Pass : public ScriptPass
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log(" run 'abc' with '-dff -D 1' options\n");
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log("\n");
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log(" -noccu2\n");
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log(" do not use CCU2 cells in output netlist\n");
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@ -290,7 +290,7 @@ struct SynthEcp5Pass : public ScriptPass
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else
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run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
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if (retime || help_mode)
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run("abc -dff", "(only if -retime)");
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run("abc -dff -D 1", "(only if -retime)");
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}
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if (check_label("map_ffs"))
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|
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@ -58,7 +58,7 @@ struct SynthEfinixPass : public ScriptPass
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log(" run 'abc' with '-dff -D 1' options\n");
|
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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@ -164,7 +164,7 @@ struct SynthEfinixPass : public ScriptPass
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run("opt -undriven -fine");
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run("techmap -map +/techmap.v -map +/efinix/arith_map.v");
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if (retime || help_mode)
|
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run("abc -dff", "(only if -retime)");
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run("abc -dff -D 1", "(only if -retime)");
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}
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|
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if (check_label("map_ffs"))
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|
|
|
@ -62,16 +62,16 @@ struct SynthGowinPass : public ScriptPass
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log(" do not flatten design before synthesis\n");
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||||
log("\n");
|
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log(" -retime\n");
|
||||
log(" run 'abc' with -dff option\n");
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||||
log(" run 'abc' with '-dff -D 1' options\n");
|
||||
log("\n");
|
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log(" -nowidelut\n");
|
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log(" do not use muxes to implement LUTs larger than LUT4s\n");
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||||
log("\n");
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log(" -noiopads\n");
|
||||
log(" do not emit IOB at top level ports\n");
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log("\n");
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||||
log(" -abc9\n");
|
||||
log(" use new ABC9 flow (EXPERIMENTAL)\n");
|
||||
//log("\n");
|
||||
//log(" -abc9\n");
|
||||
//log(" use new ABC9 flow (EXPERIMENTAL)\n");
|
||||
log("\n");
|
||||
log("\n");
|
||||
log("The following commands are executed by this synthesis command:\n");
|
||||
|
@ -144,10 +144,10 @@ struct SynthGowinPass : public ScriptPass
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|||
nowidelut = true;
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||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-abc9") {
|
||||
abc9 = true;
|
||||
continue;
|
||||
}
|
||||
//if (args[argidx] == "-abc9") {
|
||||
// abc9 = true;
|
||||
// continue;
|
||||
//}
|
||||
if (args[argidx] == "-noiopads") {
|
||||
noiopads = true;
|
||||
continue;
|
||||
|
@ -209,7 +209,7 @@ struct SynthGowinPass : public ScriptPass
|
|||
run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
|
||||
run("techmap -map +/techmap.v");
|
||||
if (retime || help_mode)
|
||||
run("abc -dff", "(only if -retime)");
|
||||
run("abc -dff -D 1", "(only if -retime)");
|
||||
run("splitnets");
|
||||
}
|
||||
|
||||
|
@ -227,13 +227,13 @@ struct SynthGowinPass : public ScriptPass
|
|||
|
||||
if (check_label("map_luts"))
|
||||
{
|
||||
if (nowidelut && abc9) {
|
||||
/*if (nowidelut && abc9) {
|
||||
run("abc9 -lut 4");
|
||||
} else if (nowidelut && !abc9) {
|
||||
} else*/ if (nowidelut && !abc9) {
|
||||
run("abc -lut 4");
|
||||
} else if (!nowidelut && abc9) {
|
||||
} else /*if (!nowidelut && abc9) {
|
||||
run("abc9 -lut 4:8");
|
||||
} else if (!nowidelut && !abc9) {
|
||||
} else*/ if (!nowidelut && !abc9) {
|
||||
run("abc -lut 4:8");
|
||||
}
|
||||
run("clean");
|
||||
|
|
|
@ -59,7 +59,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
|
|||
log(" do not flatten design before synthesis\n");
|
||||
log("\n");
|
||||
log(" -retime\n");
|
||||
log(" run 'abc' with -dff option\n");
|
||||
log(" run 'abc' with '-dff -D 1' options\n");
|
||||
log("\n");
|
||||
log("\n");
|
||||
log("The following commands are executed by this synthesis command:\n");
|
||||
|
@ -165,7 +165,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
|
|||
run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
|
||||
run("opt -fast");
|
||||
if (retime || help_mode)
|
||||
run("abc -dff", "(only if -retime)");
|
||||
run("abc -dff -D 1", "(only if -retime)");
|
||||
}
|
||||
|
||||
if (check_label("map_luts"))
|
||||
|
|
|
@ -65,7 +65,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
log(" do not flatten design before synthesis\n");
|
||||
log("\n");
|
||||
log(" -retime\n");
|
||||
log(" run 'abc' with -dff option\n");
|
||||
log(" run 'abc' with '-dff -D 1' options\n");
|
||||
log("\n");
|
||||
log(" -nocarry\n");
|
||||
log(" do not use SB_CARRY cells in output netlist\n");
|
||||
|
@ -316,7 +316,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
|
||||
}
|
||||
if (retime || help_mode)
|
||||
run(abc + " -dff", "(only if -retime)");
|
||||
run(abc + " -dff -D 1", "(only if -retime)");
|
||||
run("ice40_opt");
|
||||
}
|
||||
|
||||
|
|
|
@ -71,7 +71,7 @@ struct SynthIntelPass : public ScriptPass {
|
|||
log(" do not flatten design before synthesis\n");
|
||||
log("\n");
|
||||
log(" -retime\n");
|
||||
log(" run 'abc' with -dff option\n");
|
||||
log(" run 'abc' with '-dff -D 1' options\n");
|
||||
log("\n");
|
||||
log("The following commands are executed by this synthesis command:\n");
|
||||
help_script();
|
||||
|
@ -210,7 +210,7 @@ struct SynthIntelPass : public ScriptPass {
|
|||
run("clean -purge");
|
||||
run("setundef -undriven -zero");
|
||||
if (retime || help_mode)
|
||||
run("abc -markgroups -dff", "(only if -retime)");
|
||||
run("abc -markgroups -dff -D 1", "(only if -retime)");
|
||||
}
|
||||
|
||||
if (check_label("map_luts")) {
|
||||
|
|
|
@ -67,7 +67,7 @@ struct SynthSf2Pass : public ScriptPass
|
|||
log(" insert direct PAD->global_net buffers\n");
|
||||
log("\n");
|
||||
log(" -retime\n");
|
||||
log(" run 'abc' with -dff option\n");
|
||||
log(" run 'abc' with '-dff -D 1' options\n");
|
||||
log("\n");
|
||||
log("\n");
|
||||
log("The following commands are executed by this synthesis command:\n");
|
||||
|
@ -181,7 +181,7 @@ struct SynthSf2Pass : public ScriptPass
|
|||
run("opt -undriven -fine");
|
||||
run("techmap -map +/techmap.v -map +/sf2/arith_map.v");
|
||||
if (retime || help_mode)
|
||||
run("abc -dff", "(only if -retime)");
|
||||
run("abc -dff -D 1", "(only if -retime)");
|
||||
}
|
||||
|
||||
if (check_label("map_ffs"))
|
||||
|
|
|
@ -2315,7 +2315,7 @@ module DSP48E1 (
|
|||
endfunction
|
||||
|
||||
initial begin
|
||||
`ifdef __ICARUS__
|
||||
`ifndef YOSYS
|
||||
if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value");
|
||||
if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value");
|
||||
if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value");
|
||||
|
@ -2478,12 +2478,12 @@ module DSP48E1 (
|
|||
case (OPMODEr[1:0])
|
||||
2'b00: X = 48'b0;
|
||||
2'b01: begin X = $signed(Mrx);
|
||||
`ifdef __ICARUS__
|
||||
`ifndef YOSYS
|
||||
if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01");
|
||||
`endif
|
||||
end
|
||||
2'b10: begin X = P;
|
||||
`ifdef __ICARUS__
|
||||
`ifndef YOSYS
|
||||
if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10");
|
||||
`endif
|
||||
end
|
||||
|
@ -2495,7 +2495,7 @@ module DSP48E1 (
|
|||
case (OPMODEr[3:2])
|
||||
2'b00: Y = 48'b0;
|
||||
2'b01: begin Y = 48'b0; // FIXME: more accurate partial product modelling?
|
||||
`ifdef __ICARUS__
|
||||
`ifndef YOSYS
|
||||
if (OPMODEr[1:0] != 2'b01) $fatal(1, "OPMODEr[1:0] must be 2'b01 when OPMODEr[3:2] is 2'b01");
|
||||
`endif
|
||||
end
|
||||
|
@ -2509,13 +2509,13 @@ module DSP48E1 (
|
|||
3'b000: Z = 48'b0;
|
||||
3'b001: Z = PCIN;
|
||||
3'b010: begin Z = P;
|
||||
`ifdef __ICARUS__
|
||||
`ifndef YOSYS
|
||||
if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010");
|
||||
`endif
|
||||
end
|
||||
3'b011: Z = Cr;
|
||||
3'b100: begin Z = P;
|
||||
`ifdef __ICARUS__
|
||||
`ifndef YOSYS
|
||||
if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100");
|
||||
if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100");
|
||||
`endif
|
||||
|
|
|
@ -108,7 +108,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
log(" flatten design before synthesis\n");
|
||||
log("\n");
|
||||
log(" -retime\n");
|
||||
log(" run 'abc' with -dff option\n");
|
||||
log(" run 'abc' with '-dff -D 1' options\n");
|
||||
log("\n");
|
||||
log(" -abc9\n");
|
||||
log(" use new ABC9 flow (EXPERIMENTAL)\n");
|
||||
|
@ -550,9 +550,9 @@ struct SynthXilinxPass : public ScriptPass
|
|||
}
|
||||
else {
|
||||
if (nowidelut)
|
||||
run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
|
||||
run("abc -luts 2:2,3,6:5" + string(retime ? " -dff -D 1" : ""));
|
||||
else
|
||||
run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
|
||||
run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff -D 1" : ""));
|
||||
}
|
||||
run("clean");
|
||||
|
||||
|
|
Loading…
Reference in New Issue