mirror of https://github.com/YosysHQ/yosys.git
Add pattern detection support for DSP48E1 model, check against vendor
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@ -498,8 +498,8 @@ module DSP48E1 (
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output reg MULTSIGNOUT,
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output OVERFLOW,
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output reg signed [47:0] P,
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output PATTERNBDETECT,
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output PATTERNDETECT,
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output reg PATTERNBDETECT,
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output reg PATTERNDETECT,
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output [47:0] PCOUT,
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output UNDERFLOW,
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input signed [29:0] A,
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@ -575,10 +575,8 @@ module DSP48E1 (
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initial begin
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`ifdef __ICARUS__
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if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value");
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//if (PREG != 0) $fatal(1, "Unsupported PREG value");
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if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value");
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if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value");
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if (USE_PATTERN_DETECT != "NO_PATDET") $fatal(1, "Unsupported USE_PATTERN_DETECT value");
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if (USE_SIMD != "ONE48" && USE_SIMD != "TWO24" && USE_SIMD != "FOUR12") $fatal(1, "Unsupported USE_SIMD value");
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if (IS_ALUMODE_INVERTED != 4'b0) $fatal(1, "Unsupported IS_ALUMODE_INVERTED value");
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if (IS_CARRYIN_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CARRYIN_INVERTED value");
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@ -897,4 +895,45 @@ module DSP48E1 (
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assign PCOUT = P;
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generate
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wire PATTERNDETECTd, PATTERNBDETECTd;
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if (USE_PATTERN_DETECT == "PATDET") begin
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// TODO: Support SEL_PATTERN != "PATTERN" and SEL_MASK != "MASK
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assign PATTERNDETECTd = &(~(Pd ^ PATTERN) | MASK);
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assign PATTERNBDETECTd = &((Pd ^ PATTERN) | MASK);
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end else begin
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assign PATTERNDETECTd = 1'b1;
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assign PATTERNBDETECTd = 1'b1;
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end
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if (PREG == 1) begin
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reg PATTERNDETECTPAST, PATTERNBDETECTPAST;
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initial PATTERNDETECT = 1'b0;
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initial PATTERNBDETECT = 1'b0;
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initial PATTERNDETECTPAST = 1'b0;
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initial PATTERNBDETECTPAST = 1'b0;
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always @(posedge CLK)
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if (RSTP) begin
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PATTERNDETECT <= 1'b0;
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PATTERNBDETECT <= 1'b0;
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PATTERNDETECTPAST <= 1'b0;
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PATTERNBDETECTPAST <= 1'b0;
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end else if (CEP) begin
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PATTERNDETECT <= PATTERNDETECTd;
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PATTERNBDETECT <= PATTERNBDETECTd;
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PATTERNDETECTPAST <= PATTERNDETECT;
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PATTERNBDETECTPAST <= PATTERNBDETECT;
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end
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assign OVERFLOW = &{PATTERNDETECTPAST, ~PATTERNBDETECT, ~PATTERNDETECT};
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assign UNDERFLOW = &{PATTERNBDETECTPAST, ~PATTERNBDETECT, ~PATTERNDETECT};
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end else begin
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always @* begin
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PATTERNDETECT = PATTERNDETECTd;
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PATTERNBDETECT = PATTERNBDETECTd;
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end
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assign OVERFLOW = 1'bx, UNDERFLOW = 1'bx;
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end
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endgenerate
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endmodule
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@ -4,10 +4,10 @@ sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v >
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if [ ! -f "test_dsp_model_ref.v" ]; then
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cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v
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fi
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for tb in simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \
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for tb in macc_overflow_underflow \
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simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \
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mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \
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mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc mult_inreg_preadd_nocasc \
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mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc mult_inreg_preadd_nocasc
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do
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iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v
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vvp -N ./test_dsp_model
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@ -81,6 +81,26 @@ module testbench;
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_PATTERNDETECT !== PATTERNDETECT) begin
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$display("ERROR at %1t: REF_PATTERNDETECT=%b UUT_PATTERNDETECT=%b DIFF=%b REF_P=%b P=%b", $time, REF_PATTERNDETECT, PATTERNDETECT, REF_PATTERNDETECT ^ PATTERNDETECT, REF_P, P);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_PATTERNBDETECT !== PATTERNBDETECT) begin
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$display("ERROR at %1t: REF_PATTERNBDETECT=%b UUT_PATTERNBDETECT=%b DIFF=%b", $time, REF_PATTERNBDETECT, PATTERNBDETECT, REF_PATTERNBDETECT ^ PATTERNBDETECT);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_OVERFLOW !== OVERFLOW) begin
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$display("ERROR at %1t: REF_OVERFLOW=%b UUT_OVERFLOW=%b DIFF=%b", $time, REF_OVERFLOW, OVERFLOW, REF_OVERFLOW ^ OVERFLOW);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_UNDERFLOW !== UNDERFLOW) begin
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$display("ERROR at %1t: REF_UNDERFLOW=%b UUT_UNDERFLOW=%b DIFF=%b", $time, REF_UNDERFLOW, UNDERFLOW, REF_UNDERFLOW ^ UNDERFLOW);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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#3;
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end
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endtask
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@ -594,4 +614,39 @@ module simd24_preadd_noreg_nocasc;
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.IS_INMODE_INVERTED (5'b0),
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.IS_OPMODE_INVERTED (7'b0)
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) testbench ();
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endmodule
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endmodule
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module macc_overflow_underflow;
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testbench #(
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.ACASCREG (0),
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.ADREG (0),
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.ALUMODEREG (0),
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.AREG (0),
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.AUTORESET_PATDET ("NO_RESET"),
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.A_INPUT ("DIRECT"),
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.BCASCREG (0),
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.BREG (0),
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.B_INPUT ("DIRECT"),
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.CARRYINREG (0),
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.CARRYINSELREG (0),
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.CREG (0),
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.DREG (0),
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.INMODEREG (0),
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.MREG (0),
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.OPMODEREG (0),
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.PREG (1),
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.SEL_MASK ("MASK"),
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.SEL_PATTERN ("PATTERN"),
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.USE_DPORT ("FALSE"),
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.USE_MULT ("DYNAMIC"),
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.USE_PATTERN_DETECT ("PATDET"),
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.USE_SIMD ("ONE48"),
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.MASK (48'h1FFFFFFFFFFF),
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.PATTERN (48'h000000000000),
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.IS_ALUMODE_INVERTED(4'b0),
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.IS_CARRYIN_INVERTED(1'b0),
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.IS_CLK_INVERTED (1'b0),
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.IS_INMODE_INVERTED (5'b0),
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.IS_OPMODE_INVERTED (7'b0)
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) testbench ();
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endmodule
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