riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Ohmilord this wasn't added all this time!?!

This commit is contained in:
Eddie Hung 2019-10-04 10:34:16 -07:00
parent 2ed2e9c3e8
commit c0f54d3fd5
1 changed files with 29 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
techlibs/ice40/abc_model.v Normal file
View File

@ -0,0 +1,29 @@
(* abc9_box_id = 1, lib_whitebox *)
module \$__ICE40_CARRY_WRAPPER (
(* abc_carry *)
output CO,
output O,
input A, B,
(* abc_carry *)
input CI,
input I0, I3
);
parameter LUT = 0;
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
SB_LUT4 #(
.LUT_INIT(LUT)
) adder (
.I0(I0),
.I1(A),
.I2(B),
.I3(I3),
.O(O)
);
endmodule