mirror of https://github.com/YosysHQ/yosys.git
Rename $currQ to $abc9_currQ
This commit is contained in:
Eddie Hung
parent
2cb2116b4c
commit
b2e34f932a
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@ -479,11 +479,11 @@ struct XAigerWriter
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}
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}
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// Connect <cell>.$currQ (inserted by abc9_map.v) as an input to the flop box
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// Connect <cell>.$abc9_currQ (inserted by abc9_map.v) as an input to the flop box
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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SigSpec rhs = module->wire(stringf("%s.$currQ", cell->name.c_str()));
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SigSpec rhs = module->wire(stringf("%s.$abc9_currQ", cell->name.c_str()));
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if (rhs.empty())
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log_error("'%s.$currQ' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
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log_error("'%s.$abc9_currQ' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
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int offset = 0;
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for (auto b : rhs) {
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@ -496,7 +496,7 @@ struct XAigerWriter
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else
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alias_map[b] = I;
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}
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co_bits.emplace_back(b, cell, "\\$currQ", offset++, 0);
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co_bits.emplace_back(b, cell, "\\$abc9_currQ", offset++, 0);
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unused_bits.erase(b);
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}
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}
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@ -787,7 +787,7 @@ struct XAigerWriter
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}
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// For flops only, create an extra 1-bit input that drives a new wire
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// called "<cell>.$currQ" that is used below
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// called "<cell>.$abc9_currQ" that is used below
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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log_assert(holes_cell);
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@ -799,7 +799,7 @@ struct XAigerWriter
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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}
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Wire *w = holes_module->addWire(stringf("%s.$currQ", cell->name.c_str()));
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Wire *w = holes_module->addWire(stringf("%s.$abc9_currQ", cell->name.c_str()));
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holes_module->connect(w, holes_wire);
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}
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@ -884,9 +884,9 @@ struct XAigerWriter
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log_assert(pos != std::string::npos);
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IdString driver = Q.wire->name.substr(0, pos);
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// And drive the signal that was previously driven by "DFF.Q" (typically
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// used to implement clock-enable functionality) with the "<cell>.$currQ"
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// used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
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// wire (which itself is driven an input port) we inserted above
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Wire *currQ = holes_module->wire(stringf("%s.$currQ", driver.c_str()));
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Wire *currQ = holes_module->wire(stringf("%s.$abc9_currQ", driver.c_str()));
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log_assert(currQ);
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holes_module->connect(Q, currQ);
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continue;
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@ -35,34 +35,34 @@
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// order to extract the combinatorial control logic left behind.
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// Specifically, a simulation model similar to the one below:
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//
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// ++===================================++
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// || Sim model ||
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// || /\/\/\/\ ||
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// D -->>-----< > +------+ ||
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// R -->>-----< Comb. > |$_DFF_| ||
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// CE -->>-----< logic >-----| [NP]_|---+---->>-- Q
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// || +--< > +------+ | ||
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// || | \/\/\/\/ | ||
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// || | | ||
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// || +----------------------------+ ||
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// || ||
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// ++===================================++
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// ++===================================++
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// || Sim model ||
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// || /\/\/\/\ ||
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// D -->>-----< > +------+ ||
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// R -->>-----< Comb. > |$_DFF_| ||
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// CE -->>-----< logic >-----| [NP]_|---+---->>-- Q
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// || +--< > +------+ | ||
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// || | \/\/\/\/ | ||
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// || | | ||
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// || +----------------------------+ ||
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// || ||
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// ++===================================++
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//
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// is transformed into:
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//
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// ++==================++
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// || Comb box ||
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// || ||
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// || /\/\/\/\ ||
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// D -->>-----< > || +------+
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// R -->>-----< Comb. > || |$_ABC_|
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// CE -->>-----< logic >--->>-- $nextQ --| FF_ |--+-->> Q
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// $currQ +-->>-----< > || +------+ |
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// | || \/\/\/\/ || |
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// | || || |
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// | ++==================++ |
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// | |
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// +----------------------------------------------+
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// ++==================++
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// || Comb box ||
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// || ||
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// || /\/\/\/\ ||
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// D -->>-----< > || +------+
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// R -->>-----< Comb. > || |$_ABC_|
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// CE -->>-----< logic >--->>-- $nextQ --| FF_ |--+-->> Q
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// $abc9_currQ +-->>-----< > || +------+ |
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// | || \/\/\/\/ || |
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// | || || |
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// | ++==================++ |
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// | |
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// +----------------------------------------------+
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//
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// The purpose of the following FD* rules are to wrap the flop with:
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// (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
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@ -74,7 +74,7 @@
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// (c) a special _TECHMAP_REPLACE_.$abc9_control that captures the control
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// domain (which, combined with this cell type, encodes to `abc9' which
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// flops may be merged together)
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// (d) a special _TECHMAP_REPLACE_.$currQ wire that will be used for feedback
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// (d) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
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// into the (combinatorial) FD* cell to facilitate clock-enable behaviour
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module FDRE (output reg Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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@ -95,7 +95,7 @@ module FDRE (output reg Q, input C, CE, D, R);
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// Special signals
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
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wire _TECHMAP_REPLACE_.$currQ = Q;
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wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
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endmodule
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module FDRE_1 (output reg Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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@ -110,7 +110,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
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// Special signals
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
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wire _TECHMAP_REPLACE_.$currQ = Q;
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wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
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endmodule
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module FDCE (output reg Q, input C, CE, D, CLR);
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@ -118,7 +118,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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wire $nextQ, $currQ;
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wire $nextQ, $abc9_currQ;
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FDCE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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@ -131,19 +131,19 @@ module FDCE (output reg Q, input C, CE, D, CLR);
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// here but captured by
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// $__ABC9_ASYNC below
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
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// Since this is an async flop, async behaviour is also dealt with
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// using the $_ABC9_ASYNC box by abc9_map.v
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\$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
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\$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
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// Special signals
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
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wire _TECHMAP_REPLACE_.$currQ = $currQ;
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wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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endmodule
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module FDCE_1 (output reg Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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wire $nextQ, $currQ;
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wire $nextQ, $abc9_currQ;
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FDCE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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@ -153,13 +153,13 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
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// here but captured by
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// $__ABC9_ASYNC below
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
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\$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
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\$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(Q));
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// Special signals
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
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wire _TECHMAP_REPLACE_.$currQ = $currQ;
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wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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endmodule
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module FDPE (output reg Q, input C, CE, D, PRE);
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@ -167,7 +167,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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wire $nextQ, $currQ;
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wire $nextQ, $abc9_currQ;
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FDPE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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@ -180,17 +180,17 @@ module FDPE (output reg Q, input C, CE, D, PRE);
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// here but captured by
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// $__ABC9_ASYNC below
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
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\$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
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\$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
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// Special signals
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
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wire _TECHMAP_REPLACE_.$currQ = $currQ;
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wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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endmodule
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module FDPE_1 (output reg Q, input C, CE, D, PRE);
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parameter [0:0] INIT = 1'b0;
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wire $nextQ, $currQ;
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wire $nextQ, $abc9_currQ;
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FDPE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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@ -200,13 +200,13 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
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// here but captured by
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// $__ABC9_ASYNC below
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
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\$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
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\$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(Q));
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// Special signals
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
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wire _TECHMAP_REPLACE_.$currQ = $currQ;
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wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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endmodule
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module FDSE (output reg Q, input C, CE, D, S);
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@ -228,7 +228,7 @@ module FDSE (output reg Q, input C, CE, D, S);
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// Special signals
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
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wire _TECHMAP_REPLACE_.$currQ = Q;
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wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
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endmodule
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module FDSE_1 (output reg Q, input C, CE, D, S);
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parameter [0:0] INIT = 1'b0;
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@ -243,7 +243,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S);
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// Special signals
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
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wire _TECHMAP_REPLACE_.$currQ = Q;
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wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
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endmodule
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module RAM32X1D (
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