mirror of https://github.com/YosysHQ/yosys.git
abc -> abc9
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@ -481,13 +481,13 @@ struct SynthXilinxPass : public ScriptPass
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"will use timing for 'xc7' instead.\n", family.c_str());
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run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
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run("read_verilog -icells -lib +/xilinx/abc9_model.v");
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std::string abc9_opts = " -box +/xilinx/abc_xc7.box";
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std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
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abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
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abc9_opts += " -nomfs";
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if (nowidelut)
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abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut";
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abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
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else
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abc9_opts += " -lut +/xilinx/abc_xc7.lut";
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abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
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run("abc9" + abc9_opts);
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}
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else {
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