mirror of https://github.com/YosysHQ/yosys.git
Really get rid of 'opt_expr -fine' by being explicit
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@ -148,8 +148,17 @@ module _80_mul (A, B, Y);
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// reduction' approach also exists...
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if (i == 0)
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assign partial_sum[i] = partial[i];
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else
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assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
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else begin
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// Rewrite the following statement explicitly in order
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// to save on a call to 'opt_expr -fine' which would
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// optimise away the '<<' op and trim size of adder
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//assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
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wire [Y_WIDTH-1:0] shifted_sum = {partial[i], {i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}};
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assign partial_sum[i] = {
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partial_sum[i-1][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0],
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shifted_sum[Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]
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};
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end
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end
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\$__mul #(
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@ -163,7 +172,12 @@ module _80_mul (A, B, Y);
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.B(B),
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.Y(last_partial)
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);
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assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
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//assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
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wire [Y_WIDTH-1:0] shifted_sum = {last_partial, {n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}};
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assign partial_sum[n] = {
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partial_sum[n-1][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0],
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shifted_sum[Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]
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};
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assign Y = partial_sum[n];
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end
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else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
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@ -199,8 +213,16 @@ module _80_mul (A, B, Y);
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// reduction' approach also exists...
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if (i == 0)
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assign partial_sum[i] = partial[i];
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else
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assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
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else begin
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// Rewrite the following statement explicitly in order
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// to save on a call to 'opt_expr -fine' which would
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// optimise away the '<<' op and trim size of adder
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wire [Y_WIDTH-1:0] shifted_sum = {partial[i], {i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}};
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assign partial_sum[i] = {
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partial_sum[i-1][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0],
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shifted_sum[Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]
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};
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end
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end
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\$__mul #(
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@ -214,7 +236,12 @@ module _80_mul (A, B, Y);
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.B(B[B_WIDTH-1 -: last_B_WIDTH]),
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.Y(last_partial)
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);
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assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
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//assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
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wire [Y_WIDTH-1:0] shifted_sum = {last_partial, {n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}};
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assign partial_sum[n] = {
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partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0],
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shifted_sum[Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]
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};
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assign Y = partial_sum[n];
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end
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else begin
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@ -325,9 +325,6 @@ struct SynthXilinxPass : public ScriptPass
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if (!nodsp || help_mode) {
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// NB: Xilinx multipliers are signed only
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run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
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// Necessary for optimising away $shl cells, as well as $add cells
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// that have inputs with 1'b0 LSBs
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run("opt_expr -fine", " (skip if '-nodsp')");
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run("xilinx_dsp", " (skip if '-nodsp')");
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run("chtype -set $mul t:$__soft_mul"," (skip if '-nodsp')");
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}
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