mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1617 from YosysHQ/eddie/abc9_dsp_refactor
Refactor abc9's DSP48E1 handling
This commit is contained in:
Eddie Hung
GitHub
commit
66698cb6fd
2
Makefile
2
Makefile
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@ -128,7 +128,7 @@ bumpversion:
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# is just a symlink to your actual ABC working directory, as 'make mrproper'
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# will remove the 'abc' directory and you do not want to accidentally
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# delete your work on ABC..
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ABCREV = 623b5e8
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ABCREV = f6dc4a5
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ABCPULL = 1
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ABCURL ?= https://github.com/berkeley-abc/abc
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ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1
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@ -282,244 +282,119 @@ module DSP48E1 (
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parameter [4:0] IS_INMODE_INVERTED = 5'b0;
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parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
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parameter _TECHMAP_CELLTYPE_ = "";
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localparam techmap_guard = (_TECHMAP_CELLTYPE_ != "");
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wire [47:0] $P, $PCOUT;
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`define DSP48E1_INST(__CELL__) """
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__CELL__ #(
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.ACASCREG(ACASCREG),
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.ADREG(ADREG),
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.ALUMODEREG(ALUMODEREG),
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.AREG(AREG),
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.AUTORESET_PATDET(AUTORESET_PATDET),
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.A_INPUT(A_INPUT),
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.BCASCREG(BCASCREG),
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.BREG(BREG),
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.B_INPUT(B_INPUT),
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.CARRYINREG(CARRYINREG),
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.CARRYINSELREG(CARRYINSELREG),
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.CREG(CREG),
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.DREG(DREG),
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.INMODEREG(INMODEREG),
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.MREG(MREG),
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.OPMODEREG(OPMODEREG),
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.PREG(PREG),
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.SEL_MASK(SEL_MASK),
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.SEL_PATTERN(SEL_PATTERN),
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.USE_DPORT(USE_DPORT),
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.USE_MULT(USE_MULT),
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.USE_PATTERN_DETECT(USE_PATTERN_DETECT),
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.USE_SIMD(USE_SIMD),
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.MASK(MASK),
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.PATTERN(PATTERN),
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.IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
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.IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
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.IS_CLK_INVERTED(IS_CLK_INVERTED),
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.IS_INMODE_INVERTED(IS_INMODE_INVERTED),
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.IS_OPMODE_INVERTED(IS_OPMODE_INVERTED)
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) _TECHMAP_REPLACE_ (
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.ACOUT(ACOUT),
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.BCOUT(BCOUT),
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.CARRYCASCOUT(CARRYCASCOUT),
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.CARRYOUT(CARRYOUT),
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.MULTSIGNOUT(MULTSIGNOUT),
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.OVERFLOW(OVERFLOW),
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.P(oP),
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.PATTERNBDETECT(PATTERNBDETECT),
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.PATTERNDETECT(PATTERNDETECT),
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.PCOUT(oPCOUT),
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.UNDERFLOW(UNDERFLOW),
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.A(iA),
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.ACIN(ACIN),
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.ALUMODE(ALUMODE),
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.B(iB),
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.BCIN(BCIN),
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.C(iC),
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.CARRYCASCIN(CARRYCASCIN),
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.CARRYIN(CARRYIN),
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.CARRYINSEL(CARRYINSEL),
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.CEA1(CEA1),
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.CEA2(CEA2),
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.CEAD(CEAD),
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.CEALUMODE(CEALUMODE),
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.CEB1(CEB1),
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.CEB2(CEB2),
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.CEC(CEC),
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.CECARRYIN(CECARRYIN),
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.CECTRL(CECTRL),
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.CED(CED),
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.CEINMODE(CEINMODE),
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.CEM(CEM),
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.CEP(CEP),
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.CLK(CLK),
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.D(iD),
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.INMODE(INMODE),
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.MULTSIGNIN(MULTSIGNIN),
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.OPMODE(OPMODE),
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.PCIN(PCIN),
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.RSTA(RSTA),
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.RSTALLCARRYIN(RSTALLCARRYIN),
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.RSTALUMODE(RSTALUMODE),
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.RSTB(RSTB),
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.RSTC(RSTC),
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.RSTCTRL(RSTCTRL),
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.RSTD(RSTD),
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.RSTINMODE(RSTINMODE),
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.RSTM(RSTM),
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.RSTP(RSTP)
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);
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"""
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wire [29:0] iA;
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wire [17:0] iB;
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wire [47:0] iC;
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wire [24:0] iD;
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wire pA, pB, pC, pD, pAD, pM, pP;
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wire [47:0] oP, mP;
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wire [47:0] oPCOUT, mPCOUT;
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DSP48E1 #(
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.ACASCREG(ACASCREG),
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.ADREG(ADREG),
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.ALUMODEREG(ALUMODEREG),
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.AREG(AREG),
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.AUTORESET_PATDET(AUTORESET_PATDET),
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.A_INPUT(A_INPUT),
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.BCASCREG(BCASCREG),
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.BREG(BREG),
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.B_INPUT(B_INPUT),
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.CARRYINREG(CARRYINREG),
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.CARRYINSELREG(CARRYINSELREG),
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.CREG(CREG),
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.DREG(DREG),
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.INMODEREG(INMODEREG),
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.MREG(MREG),
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.OPMODEREG(OPMODEREG),
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.PREG(PREG),
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.SEL_MASK(SEL_MASK),
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.SEL_PATTERN(SEL_PATTERN),
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.USE_DPORT(USE_DPORT),
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.USE_MULT(USE_MULT),
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.USE_PATTERN_DETECT(USE_PATTERN_DETECT),
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.USE_SIMD(USE_SIMD),
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.MASK(MASK),
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.PATTERN(PATTERN),
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.IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
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.IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
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.IS_CLK_INVERTED(IS_CLK_INVERTED),
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.IS_INMODE_INVERTED(IS_INMODE_INVERTED),
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.IS_OPMODE_INVERTED(IS_OPMODE_INVERTED)
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) _TECHMAP_REPLACE_ (
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.ACOUT(ACOUT),
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.BCOUT(BCOUT),
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.CARRYCASCOUT(CARRYCASCOUT),
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.CARRYOUT(CARRYOUT),
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.MULTSIGNOUT(MULTSIGNOUT),
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.OVERFLOW(OVERFLOW),
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.P($P),
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.PATTERNBDETECT(PATTERNBDETECT),
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.PATTERNDETECT(PATTERNDETECT),
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.PCOUT($PCOUT),
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.UNDERFLOW(UNDERFLOW),
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.A(A),
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.ACIN(ACIN),
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.ALUMODE(ALUMODE),
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.B(B),
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.BCIN(BCIN),
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.C(C),
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.CARRYCASCIN(CARRYCASCIN),
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.CARRYIN(CARRYIN),
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.CARRYINSEL(CARRYINSEL),
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.CEA1(CEA1),
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.CEA2(CEA2),
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.CEAD(CEAD),
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.CEALUMODE(CEALUMODE),
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.CEB1(CEB1),
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.CEB2(CEB2),
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.CEC(CEC),
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.CECARRYIN(CECARRYIN),
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.CECTRL(CECTRL),
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.CED(CED),
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.CEINMODE(CEINMODE),
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.CEM(CEM),
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.CEP(CEP),
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.CLK(CLK),
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.D(D),
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.INMODE(INMODE),
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.MULTSIGNIN(MULTSIGNIN),
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.OPMODE(OPMODE),
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.PCIN(PCIN),
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.RSTA(RSTA),
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.RSTALLCARRYIN(RSTALLCARRYIN),
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.RSTALUMODE(RSTALUMODE),
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.RSTB(RSTB),
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.RSTC(RSTC),
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.RSTCTRL(RSTCTRL),
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.RSTD(RSTD),
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.RSTINMODE(RSTINMODE),
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.RSTM(RSTM),
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.RSTP(RSTP)
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);
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generate
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
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// Disconnect the A-input if MREG is enabled, since
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// combinatorial path is broken
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if (AREG == 0 && MREG == 0 && PREG == 0)
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assign iA = A, pA = 1'bx;
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else
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\$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
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if (BREG == 0 && MREG == 0 && PREG == 0)
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assign iB = B, pB = 1'bx;
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else
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\$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
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if (CREG == 0 && PREG == 0)
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assign iC = C, pC = 1'bx;
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else
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\$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
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if (DREG == 0)
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assign iD = D;
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else if (techmap_guard)
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$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
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assign pD = 1'bx;
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if (ADREG == 1 && techmap_guard)
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$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
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assign pAD = 1'bx;
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if (PREG == 0) begin
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if (MREG == 1)
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\$__ABC9_REG rM (.Q(pM));
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else
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assign pM = 1'bx;
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assign pP = 1'bx;
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end else begin
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assign pM = 1'bx;
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\$__ABC9_REG rP (.Q(pP));
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end
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wire [29:0] $A;
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wire [17:0] $B;
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wire [47:0] $C;
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wire [24:0] $D;
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if (MREG == 0 && PREG == 0)
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assign mP = oP, mPCOUT = oPCOUT;
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else
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assign mP = 1'bx, mPCOUT = 1'bx;
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\$__ABC9_DSP48E1_MULT_P_MUX muxP (
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.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
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);
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\$__ABC9_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
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.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
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);
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`DSP48E1_INST(\$__ABC9_DSP48E1_MULT )
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end
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
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// Disconnect the A-input if MREG is enabled, since
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// combinatorial path is broken
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if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
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assign iA = A, pA = 1'bx;
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else
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\$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
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if (BREG == 0 && MREG == 0 && PREG == 0)
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assign iB = B, pB = 1'bx;
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else
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\$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
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if (CREG == 0 && PREG == 0)
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assign iC = C, pC = 1'bx;
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else
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\$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
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if (DREG == 0 && ADREG == 0)
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assign iD = D, pD = 1'bx;
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else
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\$__ABC9_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
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if (PREG == 0) begin
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if (MREG == 1) begin
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assign pAD = 1'bx;
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\$__ABC9_REG rM (.Q(pM));
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end else begin
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if (ADREG == 1)
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\$__ABC9_REG rAD (.Q(pAD));
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else
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assign pAD = 1'bx;
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assign pM = 1'bx;
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if (MREG == 0 && AREG == 0) assign $A = A;
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else assign $A = 30'bx;
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if (MREG == 0 && BREG == 0) assign $B = B;
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else assign $B = 18'bx;
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if (MREG == 0 && DREG == 0) assign $D = D;
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else assign $D = 25'bx;
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if (CREG == 0) assign $C = C;
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else assign $C = 48'bx;
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end
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assign pP = 1'bx;
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end else begin
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assign pAD = 1'bx, pM = 1'bx;
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\$__ABC9_REG rP (.Q(pP));
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else begin
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assign $A = 30'bx, $B = 18'bx, $C = 48'bx, $D = 25'bx;
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end
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if (MREG == 0 && PREG == 0)
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assign mP = oP, mPCOUT = oPCOUT;
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE")
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$__ABC9_DSP48E1_MULT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE")
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$__ABC9_DSP48E1_MULT_DPORT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE")
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$__ABC9_DSP48E1 dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
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else
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assign mP = 1'bx, mPCOUT = 1'bx;
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\$__ABC9_DSP48E1_MULT_DPORT_P_MUX muxP (
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.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
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);
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\$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
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.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
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);
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`DSP48E1_INST(\$__ABC9_DSP48E1_MULT_DPORT )
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end
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
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// Disconnect the A-input if MREG is enabled, since
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// combinatorial path is broken
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if (AREG == 0 && PREG == 0)
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assign iA = A, pA = 1'bx;
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else
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\$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
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if (BREG == 0 && PREG == 0)
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assign iB = B, pB = 1'bx;
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else
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\$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
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if (CREG == 0 && PREG == 0)
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assign iC = C, pC = 1'bx;
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else
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\$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
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if (DREG == 1 && techmap_guard)
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$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
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assign pD = 1'bx;
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if (ADREG == 1 && techmap_guard)
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$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
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assign pAD = 1'bx;
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if (MREG == 1 && techmap_guard)
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$error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
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assign pM = 1'bx;
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if (PREG == 1)
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\$__ABC9_REG rP (.Q(pP));
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else
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assign pP = 1'bx;
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if (MREG == 0 && PREG == 0)
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assign mP = oP, mPCOUT = oPCOUT;
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else
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assign mP = 1'bx, mPCOUT = 1'bx;
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\$__ABC9_DSP48E1_P_MUX muxP (
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.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
|
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);
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\$__ABC9_DSP48E1_PCOUT_MUX muxPCOUT (
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.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
|
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);
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`DSP48E1_INST(\$__ABC9_DSP48E1 )
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end
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else
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$error("Invalid DSP48E1 configuration");
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$error("Invalid DSP48E1 configuration");
|
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endgenerate
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`undef DSP48E1_INST
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endmodule
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|
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@ -44,147 +44,22 @@ endmodule
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module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
|
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endmodule
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|
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// Modules used to model the comb/seq behaviour of DSP48E1
|
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// With abc9_map.v responsible for splicing the below modules
|
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// between the combinatorial DSP48E1 box (e.g. disconnecting
|
||||
// A when AREG, MREG or PREG is enabled and splicing in the
|
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// "$__ABC9_DSP48E1_REG" blackbox as "REG" in the diagram below)
|
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// this acts to first disables the combinatorial path (as there
|
||||
// is no connectivity through REG), and secondly, since this is
|
||||
// blackbox a new PI will be introduced with an arrival time of
|
||||
// zero.
|
||||
// Note: Since these "$__ABC9_DSP48E1_REG" modules are of a
|
||||
// sequential nature, they are not passed as a box to ABC and
|
||||
// (desirably) represented as PO/PIs.
|
||||
//
|
||||
// At the DSP output, we place a blackbox mux ("M" in the diagram
|
||||
// below) to capture the fact that the critical-path could come
|
||||
// from any one of its inputs.
|
||||
// In contrast to "REG", the "$__ABC9_DSP48E1_*_MUX" modules are
|
||||
// combinatorial blackboxes that do get passed to ABC.
|
||||
// The propagation delay through this box (specified in the box
|
||||
// file) captures the arrival time of the register (i.e.
|
||||
// propagation from AREG to P after clock edge), or zero delay
|
||||
// for the combinatorial path from the DSP.
|
||||
//
|
||||
// Doing so should means that ABC is able to analyse the
|
||||
// worst-case delay through to P, regardless of if it was
|
||||
// through any combinatorial paths (e.g. B, below) or an
|
||||
// internal register (A2REG).
|
||||
// However, the true value of being as complete as this is
|
||||
// questionable since if AREG=1 and BREG=0 (as below)
|
||||
// then the worse-case path would very likely be through B
|
||||
// and very unlikely to be through AREG.Q...?
|
||||
//
|
||||
// In graphical form:
|
||||
//
|
||||
// +-----+
|
||||
// +------>> REG >>----+
|
||||
// | +-----+ |
|
||||
// | |
|
||||
// | +---------+ | __
|
||||
// A >>-+X X-| | +--| \
|
||||
// | DSP48E1 |P | M |--->> P
|
||||
// | AREG=1 |-------|__/
|
||||
// B >>------| |
|
||||
// +---------+
|
||||
//
|
||||
`define ABC9_DSP48E1_MUX(__NAME__) """
|
||||
module __NAME__ (input Aq, ADq, Bq, Cq, Dq, input [47:0] I, input Mq, input [47:0] P, input Pq, output [47:0] O);
|
||||
endmodule
|
||||
"""
|
||||
(* abc9_box_id=2100 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_P_MUX )
|
||||
(* abc9_box_id=2101 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_PCOUT_MUX )
|
||||
(* abc9_box_id=2102 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_DPORT_P_MUX )
|
||||
(* abc9_box_id=2103 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX )
|
||||
(* abc9_box_id=2104 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_P_MUX )
|
||||
(* abc9_box_id=2105 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_PCOUT_MUX )
|
||||
|
||||
// Boxes used to represent the comb behaviour of various modes
|
||||
// of DSP48E1
|
||||
`define ABC9_DSP48E1(__NAME__) """
|
||||
module __NAME__ (
|
||||
output [29:0] ACOUT,
|
||||
output [17:0] BCOUT,
|
||||
output reg CARRYCASCOUT,
|
||||
output reg [3:0] CARRYOUT,
|
||||
output reg MULTSIGNOUT,
|
||||
output OVERFLOW,
|
||||
output reg signed [47:0] P,
|
||||
output PATTERNBDETECT,
|
||||
output PATTERNDETECT,
|
||||
output [47:0] PCOUT,
|
||||
output UNDERFLOW,
|
||||
input signed [29:0] A,
|
||||
input [29:0] ACIN,
|
||||
input [3:0] ALUMODE,
|
||||
input signed [17:0] B,
|
||||
input [17:0] BCIN,
|
||||
input [47:0] C,
|
||||
input CARRYCASCIN,
|
||||
input CARRYIN,
|
||||
input [2:0] CARRYINSEL,
|
||||
input CEA1,
|
||||
input CEA2,
|
||||
input CEAD,
|
||||
input CEALUMODE,
|
||||
input CEB1,
|
||||
input CEB2,
|
||||
input CEC,
|
||||
input CECARRYIN,
|
||||
input CECTRL,
|
||||
input CED,
|
||||
input CEINMODE,
|
||||
input CEM,
|
||||
input CEP,
|
||||
input CLK,
|
||||
input [24:0] D,
|
||||
input [4:0] INMODE,
|
||||
input MULTSIGNIN,
|
||||
input [6:0] OPMODE,
|
||||
input [47:0] PCIN,
|
||||
input RSTA,
|
||||
input RSTALLCARRYIN,
|
||||
input RSTALUMODE,
|
||||
input RSTB,
|
||||
input RSTC,
|
||||
input RSTCTRL,
|
||||
input RSTD,
|
||||
input RSTINMODE,
|
||||
input RSTM,
|
||||
input RSTP
|
||||
);
|
||||
parameter integer ACASCREG = 1;
|
||||
parameter integer ADREG = 1;
|
||||
parameter integer ALUMODEREG = 1;
|
||||
parameter integer AREG = 1;
|
||||
parameter AUTORESET_PATDET = "NO_RESET";
|
||||
parameter A_INPUT = "DIRECT";
|
||||
parameter integer BCASCREG = 1;
|
||||
parameter integer BREG = 1;
|
||||
parameter B_INPUT = "DIRECT";
|
||||
parameter integer CARRYINREG = 1;
|
||||
parameter integer CARRYINSELREG = 1;
|
||||
parameter integer CREG = 1;
|
||||
parameter integer DREG = 1;
|
||||
parameter integer INMODEREG = 1;
|
||||
parameter integer MREG = 1;
|
||||
parameter integer OPMODEREG = 1;
|
||||
parameter integer PREG = 1;
|
||||
parameter SEL_MASK = "MASK";
|
||||
parameter SEL_PATTERN = "PATTERN";
|
||||
parameter USE_DPORT = "FALSE";
|
||||
parameter USE_MULT = "MULTIPLY";
|
||||
parameter USE_PATTERN_DETECT = "NO_PATDET";
|
||||
parameter USE_SIMD = "ONE48";
|
||||
parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
|
||||
parameter [47:0] PATTERN = 48'h000000000000;
|
||||
parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
|
||||
parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
parameter [4:0] IS_INMODE_INVERTED = 5'b0;
|
||||
parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
|
||||
input [29:0] $A,
|
||||
input [17:0] $B,
|
||||
input [47:0] $C,
|
||||
input [24:0] $D,
|
||||
input [47:0] $P,
|
||||
input [47:0] $PCIN,
|
||||
input [47:0] $PCOUT,
|
||||
output [47:0] P,
|
||||
output [47:0] PCOUT);
|
||||
endmodule
|
||||
"""
|
||||
(* abc9_box_id=3000 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1_MULT )
|
||||
(* abc9_box_id=3001 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1_MULT_DPORT )
|
||||
(* abc9_box_id=3002 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1 )
|
||||
(* abc9_box_id=3000 *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT)
|
||||
(* abc9_box_id=3001 *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT_DPORT)
|
||||
(* abc9_box_id=3002 *) `ABC9_DSP48E1($__ABC9_DSP48E1)
|
||||
`undef ABC9_DSP48E1
|
||||
|
|
|
|||
|
|
@ -20,192 +20,24 @@
|
|||
|
||||
// ============================================================================
|
||||
|
||||
module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
|
||||
module $__ABC9_LUT6(input A, input [5:0] S, output Y);
|
||||
assign Y = A;
|
||||
endmodule
|
||||
module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
|
||||
module $__ABC9_LUT7(input A, input [6:0] S, output Y);
|
||||
assign Y = A;
|
||||
endmodule
|
||||
|
||||
module \$__ABC9_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q);
|
||||
parameter WIDTH = 1;
|
||||
assign O = I;
|
||||
endmodule
|
||||
(* techmap_celltype = "$__ABC9_DSP48E1_MULT_P_MUX $__ABC9_DSP48E1_MULT_PCOUT_MUX $__ABC9_DSP48E1_MULT_DPORT_P_MUX $__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC9_DSP48E1_P_MUX $__ABC9_DSP48E1_PCOUT_MUX" *)
|
||||
module \$__ABC9_DSP48E1_MUX (
|
||||
input Aq, Bq, Cq, Dq, ADq,
|
||||
input [47:0] I,
|
||||
input Mq,
|
||||
input [47:0] P,
|
||||
input Pq,
|
||||
output [47:0] O
|
||||
);
|
||||
assign O = I;
|
||||
endmodule
|
||||
|
||||
(* techmap_celltype = "$__ABC9_DSP48E1_MULT $__ABC9_DSP48E1_MULT_DPORT $__ABC9_DSP48E1" *)
|
||||
module \$__ABC9_DSP48E1 (
|
||||
(* techmap_autopurge *) output [29:0] ACOUT,
|
||||
(* techmap_autopurge *) output [17:0] BCOUT,
|
||||
(* techmap_autopurge *) output reg CARRYCASCOUT,
|
||||
(* techmap_autopurge *) output reg [3:0] CARRYOUT,
|
||||
(* techmap_autopurge *) output reg MULTSIGNOUT,
|
||||
(* techmap_autopurge *) output OVERFLOW,
|
||||
(* techmap_autopurge *) output reg signed [47:0] P,
|
||||
(* techmap_autopurge *) output PATTERNBDETECT,
|
||||
(* techmap_autopurge *) output PATTERNDETECT,
|
||||
(* techmap_autopurge *) output [47:0] PCOUT,
|
||||
(* techmap_autopurge *) output UNDERFLOW,
|
||||
(* techmap_autopurge *) input signed [29:0] A,
|
||||
(* techmap_autopurge *) input [29:0] ACIN,
|
||||
(* techmap_autopurge *) input [3:0] ALUMODE,
|
||||
(* techmap_autopurge *) input signed [17:0] B,
|
||||
(* techmap_autopurge *) input [17:0] BCIN,
|
||||
(* techmap_autopurge *) input [47:0] C,
|
||||
(* techmap_autopurge *) input CARRYCASCIN,
|
||||
(* techmap_autopurge *) input CARRYIN,
|
||||
(* techmap_autopurge *) input [2:0] CARRYINSEL,
|
||||
(* techmap_autopurge *) input CEA1,
|
||||
(* techmap_autopurge *) input CEA2,
|
||||
(* techmap_autopurge *) input CEAD,
|
||||
(* techmap_autopurge *) input CEALUMODE,
|
||||
(* techmap_autopurge *) input CEB1,
|
||||
(* techmap_autopurge *) input CEB2,
|
||||
(* techmap_autopurge *) input CEC,
|
||||
(* techmap_autopurge *) input CECARRYIN,
|
||||
(* techmap_autopurge *) input CECTRL,
|
||||
(* techmap_autopurge *) input CED,
|
||||
(* techmap_autopurge *) input CEINMODE,
|
||||
(* techmap_autopurge *) input CEM,
|
||||
(* techmap_autopurge *) input CEP,
|
||||
(* techmap_autopurge *) input CLK,
|
||||
(* techmap_autopurge *) input [24:0] D,
|
||||
(* techmap_autopurge *) input [4:0] INMODE,
|
||||
(* techmap_autopurge *) input MULTSIGNIN,
|
||||
(* techmap_autopurge *) input [6:0] OPMODE,
|
||||
(* techmap_autopurge *) input [47:0] PCIN,
|
||||
(* techmap_autopurge *) input RSTA,
|
||||
(* techmap_autopurge *) input RSTALLCARRYIN,
|
||||
(* techmap_autopurge *) input RSTALUMODE,
|
||||
(* techmap_autopurge *) input RSTB,
|
||||
(* techmap_autopurge *) input RSTC,
|
||||
(* techmap_autopurge *) input RSTCTRL,
|
||||
(* techmap_autopurge *) input RSTD,
|
||||
(* techmap_autopurge *) input RSTINMODE,
|
||||
(* techmap_autopurge *) input RSTM,
|
||||
(* techmap_autopurge *) input RSTP
|
||||
module $ABC9_DSP48E1(
|
||||
input [29:0] $A,
|
||||
input [17:0] $B,
|
||||
input [47:0] $C,
|
||||
input [24:0] $D,
|
||||
input [47:0] $P,
|
||||
input [47:0] $PCIN,
|
||||
input [47:0] $PCOUT,
|
||||
output [47:0] P,
|
||||
output [47:0] PCOUT
|
||||
);
|
||||
parameter integer ACASCREG = 1;
|
||||
parameter integer ADREG = 1;
|
||||
parameter integer ALUMODEREG = 1;
|
||||
parameter integer AREG = 1;
|
||||
parameter AUTORESET_PATDET = "NO_RESET";
|
||||
parameter A_INPUT = "DIRECT";
|
||||
parameter integer BCASCREG = 1;
|
||||
parameter integer BREG = 1;
|
||||
parameter B_INPUT = "DIRECT";
|
||||
parameter integer CARRYINREG = 1;
|
||||
parameter integer CARRYINSELREG = 1;
|
||||
parameter integer CREG = 1;
|
||||
parameter integer DREG = 1;
|
||||
parameter integer INMODEREG = 1;
|
||||
parameter integer MREG = 1;
|
||||
parameter integer OPMODEREG = 1;
|
||||
parameter integer PREG = 1;
|
||||
parameter SEL_MASK = "MASK";
|
||||
parameter SEL_PATTERN = "PATTERN";
|
||||
parameter USE_DPORT = "FALSE";
|
||||
parameter USE_MULT = "MULTIPLY";
|
||||
parameter USE_PATTERN_DETECT = "NO_PATDET";
|
||||
parameter USE_SIMD = "ONE48";
|
||||
parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
|
||||
parameter [47:0] PATTERN = 48'h000000000000;
|
||||
parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
|
||||
parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
parameter [4:0] IS_INMODE_INVERTED = 5'b0;
|
||||
parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
|
||||
|
||||
DSP48E1 #(
|
||||
.ACASCREG(ACASCREG),
|
||||
.ADREG(ADREG),
|
||||
.ALUMODEREG(ALUMODEREG),
|
||||
.AREG(AREG),
|
||||
.AUTORESET_PATDET(AUTORESET_PATDET),
|
||||
.A_INPUT(A_INPUT),
|
||||
.BCASCREG(BCASCREG),
|
||||
.BREG(BREG),
|
||||
.B_INPUT(B_INPUT),
|
||||
.CARRYINREG(CARRYINREG),
|
||||
.CARRYINSELREG(CARRYINSELREG),
|
||||
.CREG(CREG),
|
||||
.DREG(DREG),
|
||||
.INMODEREG(INMODEREG),
|
||||
.MREG(MREG),
|
||||
.OPMODEREG(OPMODEREG),
|
||||
.PREG(PREG),
|
||||
.SEL_MASK(SEL_MASK),
|
||||
.SEL_PATTERN(SEL_PATTERN),
|
||||
.USE_DPORT(USE_DPORT),
|
||||
.USE_MULT(USE_MULT),
|
||||
.USE_PATTERN_DETECT(USE_PATTERN_DETECT),
|
||||
.USE_SIMD(USE_SIMD),
|
||||
.MASK(MASK),
|
||||
.PATTERN(PATTERN),
|
||||
.IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
|
||||
.IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
|
||||
.IS_CLK_INVERTED(IS_CLK_INVERTED),
|
||||
.IS_INMODE_INVERTED(IS_INMODE_INVERTED),
|
||||
.IS_OPMODE_INVERTED(IS_OPMODE_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.ACOUT(ACOUT),
|
||||
.BCOUT(BCOUT),
|
||||
.CARRYCASCOUT(CARRYCASCOUT),
|
||||
.CARRYOUT(CARRYOUT),
|
||||
.MULTSIGNOUT(MULTSIGNOUT),
|
||||
.OVERFLOW(OVERFLOW),
|
||||
.P(P),
|
||||
.PATTERNBDETECT(PATTERNBDETECT),
|
||||
.PATTERNDETECT(PATTERNDETECT),
|
||||
.PCOUT(PCOUT),
|
||||
.UNDERFLOW(UNDERFLOW),
|
||||
.A(A),
|
||||
.ACIN(ACIN),
|
||||
.ALUMODE(ALUMODE),
|
||||
.B(B),
|
||||
.BCIN(BCIN),
|
||||
.C(C),
|
||||
.CARRYCASCIN(CARRYCASCIN),
|
||||
.CARRYIN(CARRYIN),
|
||||
.CARRYINSEL(CARRYINSEL),
|
||||
.CEA1(CEA1),
|
||||
.CEA2(CEA2),
|
||||
.CEAD(CEAD),
|
||||
.CEALUMODE(CEALUMODE),
|
||||
.CEB1(CEB1),
|
||||
.CEB2(CEB2),
|
||||
.CEC(CEC),
|
||||
.CECARRYIN(CECARRYIN),
|
||||
.CECTRL(CECTRL),
|
||||
.CED(CED),
|
||||
.CEINMODE(CEINMODE),
|
||||
.CEM(CEM),
|
||||
.CEP(CEP),
|
||||
.CLK(CLK),
|
||||
.D(D),
|
||||
.INMODE(INMODE),
|
||||
.MULTSIGNIN(MULTSIGNIN),
|
||||
.OPMODE(OPMODE),
|
||||
.PCIN(PCIN),
|
||||
.RSTA(RSTA),
|
||||
.RSTALLCARRYIN(RSTALLCARRYIN),
|
||||
.RSTALUMODE(RSTALUMODE),
|
||||
.RSTB(RSTB),
|
||||
.RSTC(RSTC),
|
||||
.RSTCTRL(RSTCTRL),
|
||||
.RSTD(RSTD),
|
||||
.RSTINMODE(RSTINMODE),
|
||||
.RSTM(RSTM),
|
||||
.RSTP(RSTP)
|
||||
);
|
||||
assign P = $P, PCOUT = $PCOUT;
|
||||
endmodule
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -2160,9 +2160,15 @@ module DSP48E1 (
|
|||
output reg [3:0] CARRYOUT,
|
||||
output reg MULTSIGNOUT,
|
||||
output OVERFLOW,
|
||||
`ifdef YOSYS
|
||||
(* abc9_arrival = \DSP48E1.P_arrival () *)
|
||||
`endif
|
||||
output reg signed [47:0] P,
|
||||
output reg PATTERNBDETECT,
|
||||
output reg PATTERNDETECT,
|
||||
`ifdef YOSYS
|
||||
(* abc9_arrival = \DSP48E1.PCOUT_arrival () *)
|
||||
`endif
|
||||
output [47:0] PCOUT,
|
||||
output UNDERFLOW,
|
||||
input signed [29:0] A,
|
||||
|
|
@ -2235,6 +2241,77 @@ module DSP48E1 (
|
|||
parameter [4:0] IS_INMODE_INVERTED = 5'b0;
|
||||
parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
|
||||
|
||||
`ifdef YOSYS
|
||||
function integer \DSP48E1.P_arrival ;
|
||||
begin
|
||||
\DSP48E1.P_arrival = 0;
|
||||
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
|
||||
if (PREG != 0) \DSP48E1.P_arrival = 329;
|
||||
// Worst-case from CREG and MREG
|
||||
else if (CREG != 0) \DSP48E1.P_arrival = 1687;
|
||||
else if (MREG != 0) \DSP48E1.P_arrival = 1671;
|
||||
// Worst-case from AREG and BREG
|
||||
else if (AREG != 0) \DSP48E1.P_arrival = 2952;
|
||||
else if (BREG != 0) \DSP48E1.P_arrival = 2813;
|
||||
end
|
||||
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
|
||||
if (PREG != 0) \DSP48E1.P_arrival = 329;
|
||||
// Worst-case from CREG and MREG
|
||||
else if (CREG != 0) \DSP48E1.P_arrival = 1687;
|
||||
else if (MREG != 0) \DSP48E1.P_arrival = 1671;
|
||||
// Worst-case from AREG, ADREG, BREG, DREG
|
||||
else if (AREG != 0) \DSP48E1.P_arrival = 3935;
|
||||
else if (DREG != 0) \DSP48E1.P_arrival = 3908;
|
||||
else if (ADREG != 0) \DSP48E1.P_arrival = 2958;
|
||||
else if (BREG != 0) \DSP48E1.P_arrival = 2813;
|
||||
end
|
||||
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
|
||||
if (PREG != 0) \DSP48E1.P_arrival = 329;
|
||||
// Worst-case from AREG, BREG, CREG
|
||||
else if (CREG != 0) \DSP48E1.P_arrival = 1687;
|
||||
else if (AREG != 0) \DSP48E1.P_arrival = 1632;
|
||||
else if (BREG != 0) \DSP48E1.P_arrival = 1616;
|
||||
end
|
||||
//else
|
||||
// $error("Invalid DSP48E1 configuration");
|
||||
end
|
||||
endfunction
|
||||
function integer \DSP48E1.PCOUT_arrival ;
|
||||
begin
|
||||
\DSP48E1.PCOUT_arrival = 0;
|
||||
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
|
||||
if (PREG != 0) \DSP48E1.PCOUT_arrival = 435;
|
||||
// Worst-case from CREG and MREG
|
||||
else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835;
|
||||
else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819;
|
||||
// Worst-case from AREG and BREG
|
||||
else if (AREG != 0) \DSP48E1.PCOUT_arrival = 3098;
|
||||
else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960;
|
||||
end
|
||||
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
|
||||
if (PREG != 0) \DSP48E1.PCOUT_arrival = 435;
|
||||
// Worst-case from CREG and MREG
|
||||
else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835;
|
||||
else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819;
|
||||
// Worst-case from AREG, ADREG, BREG, DREG
|
||||
else if (AREG != 0) \DSP48E1.PCOUT_arrival = 4083;
|
||||
else if (DREG != 0) \DSP48E1.PCOUT_arrival = 4056;
|
||||
else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960;
|
||||
else if (ADREG != 0) \DSP48E1.PCOUT_arrival = 2859;
|
||||
end
|
||||
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
|
||||
if (PREG != 0) \DSP48E1.PCOUT_arrival = 435;
|
||||
// Worst-case from AREG, BREG, CREG
|
||||
else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835;
|
||||
else if (AREG != 0) \DSP48E1.PCOUT_arrival = 1780;
|
||||
else if (BREG != 0) \DSP48E1.PCOUT_arrival = 1765;
|
||||
end
|
||||
//else
|
||||
// $error("Invalid DSP48E1 configuration");
|
||||
end
|
||||
endfunction
|
||||
`endif
|
||||
|
||||
initial begin
|
||||
`ifndef YOSYS
|
||||
if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value");
|
||||
|
|
|
|||
Loading…
Reference in New Issue