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ecp5 to use -max_iter 1

This commit is contained in:
Eddie Hung 2019-08-20 19:18:36 -07:00
parent 55acf3120f
commit d46dc9c5b4
3 changed files with 3 additions and 4 deletions
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2
techlibs/ecp5/abc_map.v
View File

@ -13,7 +13,7 @@ module TRELLIS_DPR16X4 (
parameter [63:0] INITVAL = 64'h0000000000000000;
wire [3:0] \$DO ;
\$__ABC_DPR16X4_SEQ #(
TRELLIS_DPR16X4 #(
.WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
) _TECHMAP_REPLACE_ (
.DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),

2
techlibs/ecp5/cells_sim.v
View File

@ -113,7 +113,7 @@ module TRELLIS_DPR16X4 (
input WRE,
input WCK,
input [3:0] RAD,
output [3:0] DO
/* (* abc_arrival=<TODO> *) */ output [3:0] DO
);
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";

3
techlibs/ecp5/synth_ecp5.cc
View File

@ -280,11 +280,10 @@ struct SynthEcp5Pass : public ScriptPass
}
std::string techmap_args = "-map +/ecp5/latches_map.v";
if (abc9)
techmap_args += " -map +/ecp5/abc_map.v";
techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
run("techmap " + techmap_args);
if (abc9) {
run("read_verilog -icells -lib +/ecp5/abc_model.v");
if (nowidelut)
run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
else